rustv - A minimal, intentionally inaccurate RISC-V ISA simulator in Rust

Age	Commit message (Collapse)	Author	Files	Lines
2016-01-25	feat(cache): add callback for requesting new block	David Li	1	-0/+1

2016-01-24	Provide API to react to cache events	David Li	1	-239/+0

2016-01-17	Distinguish between memory and cache at type level	David Li	1	-0/+42

2016-01-15	Allow stalls that do not retry instruction	David Li	1	-2/+7

2016-01-14	Fix tests	David Li	1	-2/+2

2016-01-14	Convert ISA types to newtype structs	David Li	1	-39/+29

2016-01-11	Correct ReverseMmu (map 0 to present address)	David Li	1	-1/+1

2016-01-09	Fix ReverseMmu address translation	David Li	1	-1/+2

2016-01-08	Add MemoryInterface.is_address_accessible	David Li	1	-0/+13

2016-01-07	Implement halfword access	David Li	1	-6/+36

2016-01-06	Fix default read_instruction implementation	David Li	1	-1/+1

2016-01-06	Get rid of Box in memory refs	David Li	1	-1/+1

2016-01-05	Update copyright	David Li	1	-1/+1

2016-01-04	Enable loading with address translation	David Li	1	-6/+6

2016-01-04	Get rid of unused code	David Li	1	-8/+3

2016-01-04	Make memory construction from segments a method instead	David Li	1	-18/+4

2016-01-04	Fix cache sharing bug	David Li	1	-1/+5

2016-01-04	Implement initializing memory from text/data segments	David Li	1	-0/+45

2016-01-03	Add MMU to core	David Li	1	-1/+32

2016-01-03	Write value to cache as well	David Li	1	-35/+43

2016-01-03	Fix write_byte, add basic tests	David Li	1	-4/+3

2016-01-03	Add write_word, read_byte, write_byte	David Li	1	-6/+50

2016-01-01	Make MMU a trait for API user to implement	David Li	1	-3/+2

2016-01-01	Test use of cache in simulation	David Li	1	-8/+8

2016-01-01	Finish read_word for cache	David Li	1	-6/+17

2015-12-31	Finish DirectMappedCache.step	David Li	1	-19/+26

2015-12-31	Sketch impl of cache step	David Li	1	-2/+60

2015-12-30	Convert simulator to using cache	David Li	1	-16/+23

2015-12-29	Don't give cache ownership of memory	David Li	1	-3/+6

2015-12-29	Update test for new cache	David Li	1	-1/+7

2015-12-28	Specialize to direct-mapped cache	David Li	1	-21/+35

2015-12-28	Implement basic cache lookup	David Li	1	-10/+27

2015-12-27	Add GPLv3 license	David Li	1	-0/+16

2015-12-27	Fix and test cache address parsing	David Li	1	-12/+12

2015-12-27	Include fetch requests in cache	David Li	1	-6/+16

2015-12-25	Convert PC to u32	David Li	1	-6/+32

2015-12-25	Add trait for memory interface	David Li	1	-18/+50

2015-12-20	Introduce type aliases for ISA things	David Li	1	-9/+7

2015-12-20	Add Cache API	David Li	1	-5/+54

2015-12-18	Implement RV32I integer-register instructions	David Li	1	-0/+11

2015-12-16	Load and recognize a minimal set of instructions	David Li	1	-4/+11

2015-12-15	Outline the simulator	David Li	1	-0/+21