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authorDavid Li <li.davidm96@gmail.com>2016-01-25 11:39:29 -0500
committerDavid Li <li.davidm96@gmail.com>2016-01-25 11:39:53 -0500
commit0a588332811b1f45d4ae7fea74914ea29e968644 (patch)
tree94b93c189df27d353c9b60509373b7c91756c366 /src/memory.rs
parent692f250415859aea37794a1d20d89c44e62c83e3 (diff)
feat(cache): add callback for requesting new block
Diffstat (limited to 'src/memory.rs')
-rw-r--r--src/memory.rs1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/memory.rs b/src/memory.rs
index 33a9503..2a5b717 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -126,6 +126,7 @@ pub trait MemoryInterface {
pub type SharedMemory<'a> = Rc<RefCell<MemoryInterface + 'a>>;
+// TODO: rename to BijectiveMmu?
pub trait Mmu {
fn translate(&self, address: isa::Address) -> isa::Address;
}