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authorDavid Li <li.davidm96@gmail.com>2016-01-15 17:21:00 -0700
committerDavid Li <li.davidm96@gmail.com>2016-01-15 17:21:00 -0700
commit05a9968d6dafb31d0e33590d80f6eb364de50d8a (patch)
treea9ae8ef56a9d64a1405e5540dcb62df2b1c72b80 /src/memory.rs
parent4567214f23a63b4e4964433f4034240cc4fa6a4b (diff)
Allow stalls that do not retry instruction
Diffstat (limited to 'src/memory.rs')
-rw-r--r--src/memory.rs9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/memory.rs b/src/memory.rs
index b9f070b..052ffb7 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -23,7 +23,10 @@ use isa::{self, Instruction, IsaType};
pub enum MemoryError {
InvalidAddress,
CacheMiss {
+ /// How many cycles to stall
stall_cycles: u32,
+ /// Whether the load or store should be retried
+ retry: bool,
},
}
@@ -334,7 +337,7 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> {
fetch_request.data[offset as usize] = data;
fetch_request.waiting_on += 1;
},
- Err(MemoryError::CacheMiss { stall_cycles }) => {
+ Err(MemoryError::CacheMiss { stall_cycles, .. }) => {
fetch_request.cycles_left = stall_cycles;
continue;
},
@@ -401,12 +404,14 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> {
fetch_request.error = None;
return Err(MemoryError::CacheMiss {
- stall_cycles: fetch_request.cycles_left
+ stall_cycles: fetch_request.cycles_left,
+ retry: true,
});
}
Err(MemoryError::CacheMiss {
stall_cycles: stall,
+ retry: true,
})
}