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authorDavid Li <li.davidm96@gmail.com>2016-01-13 09:42:18 -0700
committerDavid Li <li.davidm96@gmail.com>2016-01-13 09:42:18 -0700
commit56bf151b4fd091360246b2cfe230997e4082b0bc (patch)
tree68648edceada6302c8896efd878e54b7b3bbea73 /src/shareable_cache.rs
parent12e3bb51af09c56f306a1a365e989e8fb96b8a99 (diff)
Start working on updating global data structures
Diffstat (limited to 'src/shareable_cache.rs')
-rw-r--r--src/shareable_cache.rs7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/shareable_cache.rs b/src/shareable_cache.rs
index 9e0725a..6ee17c3 100644
--- a/src/shareable_cache.rs
+++ b/src/shareable_cache.rs
@@ -52,7 +52,7 @@ impl<'a> ShareableCache<'a> {
if cache.borrow().is_address_accessible(address) {
// Depends on invariant: write_word completes instantly
// when the address is accessible (in-cache)
- cache.borrow_mut().write_word(address, value);
+ let _ = cache.borrow_mut().write_word(address, value);
}
}
}
@@ -76,6 +76,11 @@ impl<'a> MemoryInterface for ShareableCache<'a> {
}
fn read_word(&mut self, address: isa::Address) -> Result<isa::Word> {
+ // TODO: disallow access to high or low memory unless
+ // secondary cache is enabled. Remember: addresses are already
+ // translated
+
+ // TODO: is CacheRacer physically or virtually addressed?
if self.secondary_enabled {
let (primary_accessible, secondary_accessible) =
self.address_accessible(address);