Start working on updating global data structures

5 files changed, 82 insertions, 19 deletions

diff --git a/TODO.md b/TODO.md
index 5de3a9a..63c16ec 100644
--- a/TODO.md
+++ b/TODO.md
@@ -26,7 +26,7 @@ https://git.lidavidm.me/cacheracer/.
     - [ ] Player status
     - [ ] Core status
     - [ ] Cache info
-    - [ ] Enemy status should be inaccessible unless in sneak-attack mode
+    - [ ] Enemy memory should be inaccessible unless in sneak-attack mode
 
 ## Scoring
 
@@ -50,7 +50,7 @@ https://git.lidavidm.me/cacheracer/.
 
 - [ ] Write the header file
 - [x] Write some sample bots
-    - [ ] Publish them
+    - [x] Publish them
 - [ ] Package RISC-V toolchain
     - [ ] Find way to shrink toolchain
 - [ ] Implement debugger
diff --git a/src/globals.rs b/src/globals.rs
new file mode 100644
index 0000000..27d3bbd
--- /dev/null
+++ b/src/globals.rs
@@ -0,0 +1,58 @@
+use std::cell::RefCell;
+use std::rc::Rc;
+
+use rustv::isa;
+use rustv::memory::{Memory, MemoryInterface, Mmu};
+
+use memory_tracker::MemoryTracker;
+
+pub const HOME_STATUS: isa::Address = 0xFFF00;
+
+/// Update the various global data structures as requested by other
+/// subsystems.
+// Intended to be passed around as &'a GlobalsUpdater
+pub struct GlobalsUpdater<'a> {
+    // TODO: weak reference?
+    memory: Rc<RefCell<MemoryTracker>>,
+    mmu1: Box<Mmu + 'a>,
+    mmu2: Box<Mmu + 'a>,
+}
+
+impl<'a> GlobalsUpdater<'a> {
+    pub fn new(memory: Rc<RefCell<MemoryTracker>>,
+               mmu1: Box<Mmu + 'a>, mmu2: Box<Mmu + 'a>) -> GlobalsUpdater<'a> {
+        GlobalsUpdater {
+            memory: memory,
+            mmu1: mmu1,
+            mmu2: mmu2,
+        }
+    }
+
+    pub fn init_memory(&self) {
+        // Initialize taunt array to all -1
+        for offset in 0..(228 / 4) {
+            let address1 = self.mmu1.translate(HOME_STATUS + 28 + offset);
+            let address2 = self.mmu2.translate(HOME_STATUS + 28 + offset);
+            let _ = self.memory.borrow_mut().write_word(
+                address1,
+                (-1 as i32) as isa::Word);
+            let _ = self.memory.borrow_mut().write_word(
+                address2,
+                (-1 as i32) as isa::Word);
+        }
+    }
+
+    // TODO: how to distinguish which player?
+    pub fn fetch_tag(&self, tag: isa::Address, index: u32) {
+        // TODO: assert index is 0 or 1
+        let address = HOME_STATUS;
+    }
+
+    pub fn finish_tag(&self, tag: isa::Address, index: u32) {
+
+    }
+
+    pub fn update_score(&self, player1: i64, player2: i64) {
+
+    }
+}
diff --git a/src/main.rs b/src/main.rs
index 0667401..615a965 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -6,6 +6,7 @@ extern crate rustc_serialize;
 extern crate rustv;
 extern crate time;
 
+mod globals;
 mod memory_tracker;
 mod shareable_cache;
 mod system;
@@ -82,6 +83,7 @@ fn main() {
     let payload2 = rand::random::<u8>();
 
     let memory = MemoryTracker::new(memory, payload1, payload2);
+    // TODO: initialize global data
 
     let memory_ref = Rc::new(RefCell::new(memory));
     let cache = memory::DirectMappedCache::new(2, 64, memory_ref.clone());
@@ -118,7 +120,8 @@ fn main() {
         cores.push(core);
     }
 
-    let steppable_caches = vec![cache_ref.clone() as memory::SharedMemory, cache2_ref];
+    let steppable_caches: Vec<memory::SharedMemory> =
+        vec![cache_ref, cache2_ref];
     let system = SyscallHandler::new(memory_ref.clone(), core_caches);
     let mut simulator = simulator::Simulator::new(
         cores, memory_ref.clone(), steppable_caches, system);
@@ -129,7 +132,8 @@ fn main() {
     simulator.run_max(cycles);
     let end = time::precise_time_s();
 
-    println!("{} cycles in {:04} seconds ({} cycles/sec)", cycles, end - start, (cycles as f64) / (end - start));
+    println!("{} cycles in {:04} seconds ({} cycles/sec)",
+             cycles, end - start, (cycles as f64) / (end - start));
     let (p1, p2) = memory_ref.borrow().score();
     println!("Program 1 bytes written: {}", p1);
     println!("Program 2 bytes written: {}", p2);
diff --git a/src/shareable_cache.rs b/src/shareable_cache.rs
index 9e0725a..6ee17c3 100644
--- a/src/shareable_cache.rs
+++ b/src/shareable_cache.rs
@@ -52,7 +52,7 @@ impl<'a> ShareableCache<'a> {
         if cache.borrow().is_address_accessible(address) {
             // Depends on invariant: write_word completes instantly
             // when the address is accessible (in-cache)
-            cache.borrow_mut().write_word(address, value);
+            let _ = cache.borrow_mut().write_word(address, value);
         }
     }
 }
@@ -76,6 +76,11 @@ impl<'a> MemoryInterface for ShareableCache<'a> {
     }
 
     fn read_word(&mut self, address: isa::Address) -> Result<isa::Word> {
+        // TODO: disallow access to high or low memory unless
+        // secondary cache is enabled. Remember: addresses are already
+        // translated
+
+        // TODO: is CacheRacer physically or virtually addressed?
         if self.secondary_enabled {
             let (primary_accessible, secondary_accessible) =
                 self.address_accessible(address);
diff --git a/src/system.rs b/src/system.rs
index 4e48303..c0343bb 100644
--- a/src/system.rs
+++ b/src/system.rs
@@ -3,7 +3,7 @@ use std::cell::RefCell;
 use std::rc::Rc;
 
 use rustv::isa;
-use rustv::memory::SharedMemory;
+use rustv::memory::{Mmu, SharedMemory};
 use rustv::register_file::RegisterFile;
 use rustv::syscall;
 use rustv::trap::Trap;
@@ -27,8 +27,7 @@ impl<'a> SyscallHandler<'a> {
 }
 
 impl<'a> SyscallHandler<'a> {
-    fn prints(&mut self, core_id: usize,
-             registers: &mut RegisterFile) -> Option<Trap> {
+    fn prints(&mut self, registers: &mut RegisterFile) -> Option<Trap> {
         let mut base = registers.read_word(isa::Register::X11);
         let mut string = vec![];
 
@@ -55,23 +54,20 @@ impl<'a> SyscallHandler<'a> {
         None
     }
 
-    fn printi(&mut self, core_id: usize,
+    fn printi(&mut self,
               registers: &mut RegisterFile) -> Option<Trap> {
         println!("{}", registers.read_word(isa::Register::X11));
-
         None
     }
 
-    fn enable_secondary(&mut self, core_id: usize,
-                        registers: &mut RegisterFile) -> Option<Trap> {
+    fn enable_secondary(&mut self, core_id: usize) -> Option<Trap> {
         debug!("[syscall] [memory] Secondary cache enabled for core {}",
                core_id);
         self.caches[core_id].borrow_mut().enable_secondary();
         None
     }
 
-    fn disable_secondary(&mut self, core_id: usize,
-                         registers: &mut RegisterFile) -> Option<Trap> {
+    fn disable_secondary(&mut self, core_id: usize) -> Option<Trap> {
         debug!("[syscall] [memory] Secondary cache disabled for core {}",
                core_id);
         self.caches[core_id].borrow_mut().disable_secondary();
@@ -82,14 +78,14 @@ impl<'a> SyscallHandler<'a> {
 impl<'a> syscall::SyscallHandler for SyscallHandler<'a> {
     // TODO: is trap really appropriate here?
     fn syscall(&mut self, core_id: usize,
-               registers: &mut RegisterFile) -> Option<Trap> {
+               registers: &mut RegisterFile, mmu: &Mmu) -> Option<Trap> {
         let syscall_number = registers.read_word(isa::Register::X10);
 
         match syscall_number {
-            22 => self.prints(core_id, registers),
-            23 => self.printi(core_id, registers),
-            24 => self.enable_secondary(core_id, registers),
-            25 => self.disable_secondary(core_id, registers),
+            22 => self.prints(registers),
+            23 => self.printi(registers),
+            24 => self.enable_secondary(core_id),
+            25 => self.disable_secondary(core_id),
 
             _ => {
                 // TODO: some sort of error reporting