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-rw-r--r--src/memory.rs1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/memory.rs b/src/memory.rs
index 33a9503..2a5b717 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -126,6 +126,7 @@ pub trait MemoryInterface {
pub type SharedMemory<'a> = Rc<RefCell<MemoryInterface + 'a>>;
+// TODO: rename to BijectiveMmu?
pub trait Mmu {
fn translate(&self, address: isa::Address) -> isa::Address;
}