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A minimal, intentionally inaccurate RISC-V ISA simulator in Rust
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src
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lib.rs
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2016-01-04
Load ELF directly
David Li
1
-32
/
+23
2016-01-04
Implement initializing memory from text/data segments
David Li
1
-1
/
+32
2016-01-03
Add MMU to core
David Li
1
-2
/
+3
2016-01-03
Test writing with cache miss
David Li
1
-4
/
+21
2016-01-03
Test reading and writing cache and memory
David Li
1
-0
/
+35
2016-01-03
Fix write_byte, add basic tests
David Li
1
-1
/
+22
2016-01-01
Test use of cache in simulation
David Li
1
-2
/
+3
2015-12-30
Convert simulator to using cache
David Li
1
-1
/
+6
2015-12-29
Don't give cache ownership of memory
David Li
1
-3
/
+8
2015-12-29
Update test for new cache
David Li
1
-7
/
+4
2015-12-27
Add GPLv3 license
David Li
1
-0
/
+16
2015-12-27
Move tests to test module
David Li
1
-11
/
+16
2015-12-27
Fix and test cache address parsing
David Li
1
-0
/
+14
2015-12-25
Add trait for memory interface
David Li
1
-0
/
+1
2015-12-20
Introduce type aliases for ISA things
David Li
1
-1
/
+0
2015-12-19
Implement RV32I integer-immediate instructions
David Li
1
-1
/
+0
2015-12-18
Implement RV32I integer-register instructions
David Li
1
-6
/
+5
2015-12-16
Load and recognize a minimal set of instructions
David Li
1
-1
/
+4
2015-12-15
Load hexdump of ELF
David Li
1
-0
/
+7
2015-12-15
Outline the simulator
David Li
1
-0
/
+9