aboutsummaryrefslogtreecommitdiff
path: root/src/lib.rs
AgeCommit message (Collapse)AuthorFilesLines
2016-01-05Update copyrightDavid Li1-1/+1
2016-01-04Enable loading with address translationDavid Li1-9/+21
2016-01-04Get rid of unused codeDavid Li1-1/+1
2016-01-04Make memory construction from segments a method insteadDavid Li1-4/+3
2016-01-04Fix cache sharing bugDavid Li1-2/+4
2016-01-04Load ELF directlyDavid Li1-32/+23
2016-01-04Implement initializing memory from text/data segmentsDavid Li1-1/+32
2016-01-03Add MMU to coreDavid Li1-2/+3
2016-01-03Test writing with cache missDavid Li1-4/+21
2016-01-03Test reading and writing cache and memoryDavid Li1-0/+35
2016-01-03Fix write_byte, add basic testsDavid Li1-1/+22
2016-01-01Test use of cache in simulationDavid Li1-2/+3
2015-12-30Convert simulator to using cacheDavid Li1-1/+6
2015-12-29Don't give cache ownership of memoryDavid Li1-3/+8
2015-12-29Update test for new cacheDavid Li1-7/+4
2015-12-27Add GPLv3 licenseDavid Li1-0/+16
2015-12-27Move tests to test moduleDavid Li1-11/+16
2015-12-27Fix and test cache address parsingDavid Li1-0/+14
2015-12-25Add trait for memory interfaceDavid Li1-0/+1
2015-12-20Introduce type aliases for ISA thingsDavid Li1-1/+0
2015-12-19Implement RV32I integer-immediate instructionsDavid Li1-1/+0
2015-12-18Implement RV32I integer-register instructionsDavid Li1-6/+5
2015-12-16Load and recognize a minimal set of instructionsDavid Li1-1/+4
2015-12-15Load hexdump of ELFDavid Li1-0/+7
2015-12-15Outline the simulatorDavid Li1-0/+9