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-rw-r--r--src/memory.rs22
-rw-r--r--src/simulator.rs2
2 files changed, 17 insertions, 7 deletions
diff --git a/src/memory.rs b/src/memory.rs
index ae3b6fc..e65eb10 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -33,12 +33,20 @@ pub struct Memory {
}
#[derive(Clone)]
+struct FetchRequest {
+ cycles_left: u32,
+}
+
+#[derive(Clone)]
struct CacheBlock {
valid: bool,
tag: u32,
contents: Vec<u32>,
+ fetch_request: Option<FetchRequest>,
}
+type CacheSet = Vec<CacheBlock>;
+
// TODO: probably want different caches for different strategies, and
// investigate how LRU is implemented
// TODO: use hashtable for a way?
@@ -47,7 +55,7 @@ pub struct Cache {
num_sets: usize,
num_ways: usize,
block_words: usize,
- cache: Vec<Vec<CacheBlock>>,
+ cache: Vec<CacheSet>,
}
impl Memory {
@@ -95,15 +103,17 @@ impl MemoryInterface for Memory {
impl Cache {
pub fn new(sets: usize, ways: usize, block_words: usize) -> Cache {
+ let set = vec![CacheBlock {
+ valid: false,
+ tag: 0,
+ contents: vec![0; block_words],
+ fetch_request: None,
+ }; ways];
Cache {
num_sets: sets,
num_ways: ways,
block_words: block_words,
- cache: vec![vec![CacheBlock {
- valid: false,
- tag: 0,
- contents: vec![0; block_words],
- }; ways]; sets],
+ cache: vec![set; sets],
}
}
diff --git a/src/simulator.rs b/src/simulator.rs
index 277e52f..f91ccbc 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -75,7 +75,7 @@ impl Simulator {
};
let mut cores = vec![base_core; self.num_cores];
// hardcode GP
- cores[0].registers.write_word(isa::Register::X3, 0x10860);
+ cores[0].registers.write_word(isa::Register::X3, 0x108D0);
// hardcode SP
cores[0].registers.write_word(isa::Register::X2, 0x7FFC);
loop {