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-rw-r--r--src/cache.rs8
-rw-r--r--src/isa/funct3.rs7
-rw-r--r--src/isa/mod.rs39
-rw-r--r--src/isa/opcodes.rs2
-rw-r--r--src/lib.rs1
-rw-r--r--src/memory.rs57
-rw-r--r--src/simulator.rs87
7 files changed, 150 insertions, 51 deletions
diff --git a/src/cache.rs b/src/cache.rs
deleted file mode 100644
index 26fdc18..0000000
--- a/src/cache.rs
+++ /dev/null
@@ -1,8 +0,0 @@
-// pub struct Cache {
-// }
-
-// impl Cache {
-// pub fn new(sets: usize, ways: usize, block_size: usize) -> Cache {
-
-// }
-// }
diff --git a/src/isa/funct3.rs b/src/isa/funct3.rs
index be2eafa..e74da96 100644
--- a/src/isa/funct3.rs
+++ b/src/isa/funct3.rs
@@ -16,6 +16,13 @@ pub const SRL_SRA: u32 = 0x5;
pub const OR: u32 = 0x6;
pub const AND: u32 = 0x7;
+pub const BEQ: u32 = 0b000;
+pub const BNE: u32 = 0b001;
+pub const BLT: u32 = 0b100;
+pub const BGE: u32 = 0b101;
+pub const BLTU: u32 = 0b110;
+pub const BGEU: u32 = 0b111;
+
pub const LW: u32 = 0x2;
pub const SW: u32 = 0x2;
diff --git a/src/isa/mod.rs b/src/isa/mod.rs
index 0e3261b..6519a34 100644
--- a/src/isa/mod.rs
+++ b/src/isa/mod.rs
@@ -2,6 +2,12 @@ pub mod opcodes;
pub mod funct3;
pub mod funct7;
+pub type Word = u32;
+pub type SignedWord = i32;
+
+// TODO: directly encode PC as u32, as architecturally specified
+pub type Address = usize;
+
#[derive(Debug, PartialEq)]
pub enum Register {
X0 = 0,
@@ -84,6 +90,8 @@ impl Register {
#[derive(Copy, Clone, Debug)]
pub struct Instruction {
+ // TODO: rename word to something correct - instructions are not always a
+ // word
word: u32,
}
@@ -122,14 +130,31 @@ impl Instruction {
Register::from_num((self.word >> 20) & 0x1F)
}
- pub fn i_imm(&self) -> i32 {
- (self.word as i32) >> 20
+ pub fn i_imm(&self) -> SignedWord {
+ (self.word as SignedWord) >> 20
+ }
+
+ pub fn s_imm(&self) -> SignedWord {
+ let low = (self.word >> 7) & 0x1F;
+ let high = (((self.word as SignedWord) >> 25) & 0x7F) as Word;
+ ((high << 7) | low) as SignedWord
+ }
+
+ pub fn uj_imm(&self) -> SignedWord {
+ // Want zero-extension
+ let low1 = (self.word >> 21) & 0x3FF;
+ let low11 = (self.word >> 20) & 0x1;
+ let low12 = (self.word >> 12) & 0xFF;
+ // Want sign-extension
+ let low20 = (((self.word as SignedWord) >> 30) & 0x1) as Word;
+ ((low20 << 20) | (low12 << 12) | (low11 << 11) | (low1 << 1)) as SignedWord
}
- pub fn s_imm(&self) -> i32 {
- let word = self.word as i32;
- let low = (word >> 7) & 0x1F;
- let high = (word >> 25) & 0x7F;
- (high << 7) | low
+ pub fn sb_imm(&self) -> SignedWord {
+ let low1 = (self.word >> 8) & 0xF;
+ let low5 = (self.word >> 25) & 0x3F;
+ let low11 = (self.word >> 7) & 0x1;
+ let low12 = (((self.word as SignedWord) >> 31) & 0x1) as Word;
+ ((low12 << 12) | (low11 << 11) | (low5 << 5) | (low1 << 1)) as SignedWord
}
}
diff --git a/src/isa/opcodes.rs b/src/isa/opcodes.rs
index e5763e3..56b9568 100644
--- a/src/isa/opcodes.rs
+++ b/src/isa/opcodes.rs
@@ -1,6 +1,6 @@
pub const BRANCH: u32 = 0x63;
pub const JALR: u32 = 0x67;
-pub const JAL: u32 = 0x68;
+pub const JAL: u32 = 0x6F;
pub const INTEGER_IMMEDIATE: u32 = 0x13;
pub const INTEGER_REGISTER: u32 = 0x33;
pub const LOAD: u32 = 0x3;
diff --git a/src/lib.rs b/src/lib.rs
index b3d29aa..fd60531 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,7 +1,6 @@
pub mod isa;
pub mod binary;
pub mod memory;
-pub mod cache;
pub mod simulator;
#[test]
diff --git a/src/memory.rs b/src/memory.rs
index b7e3721..ffe37c4 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -1,12 +1,32 @@
-use isa::{Instruction};
+use isa::{self, Instruction};
use binary::{Binary};
pub struct Memory {
memory: Vec<u32>,
}
+#[derive(Clone)]
+struct CacheBlock {
+ valid: bool,
+ tag: u32,
+ contents: Vec<u32>,
+}
+
+// TODO: probably want different caches for different strategies, and
+// investigate how LRU is implemented
+// TODO: use hashtable for a way?
+// TODO: hashtable-based FA cache?
+pub struct Cache {
+ num_sets: usize,
+ num_ways: usize,
+ block_words: usize,
+ cache: Vec<Vec<CacheBlock>>,
+}
+
+// TODO: refactor impls into a MemoryController(?) trait
+
impl Memory {
- pub fn new(size: usize, binary: Binary) -> Memory {
+ pub fn new(size: isa::Address, binary: Binary) -> Memory {
let mut memory = binary.words.clone();
if size > memory.len() {
let remainder = size - memory.len();
@@ -17,12 +37,12 @@ impl Memory {
}
}
- pub fn read_word(&self, address: usize) -> Option<u32> {
+ pub fn read_word(&self, address: isa::Address) -> Option<isa::Word> {
// memory is word-addressed but addresses are byte-addressed
self.memory.get(address / 4).map(Clone::clone)
}
- pub fn write_word(&mut self, address: usize, value: u32) -> Option<()> {
+ pub fn write_word(&mut self, address: isa::Address, value: isa::Word) -> Option<()> {
let address = address / 4;
if address >= self.memory.len() {
None
@@ -33,7 +53,34 @@ impl Memory {
}
}
- pub fn read_instruction(&self, pc: usize) -> Option<Instruction> {
+ pub fn read_instruction(&self, pc: isa::Address) -> Option<Instruction> {
self.memory.get(pc / 4).map(Clone::clone).map(Instruction::new)
}
}
+
+impl Cache {
+ pub fn new(sets: usize, ways: usize, block_words: usize) -> Cache {
+ Cache {
+ num_sets: sets,
+ num_ways: ways,
+ block_words: block_words,
+ cache: vec![vec![CacheBlock {
+ valid: false,
+ tag: 0,
+ contents: vec![0; block_words],
+ }; ways]; sets],
+ }
+ }
+
+ fn read_word(&self, address: isa::Address) -> Option<isa::Word> {
+ None
+ }
+
+ fn write_word(&mut self, address: isa::Address, value: isa::Word) -> Option<()> {
+ None
+ }
+
+ fn invalidate(&mut self, address: isa::Address) {
+
+ }
+}
diff --git a/src/simulator.rs b/src/simulator.rs
index 8142b32..d30ae7c 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -9,12 +9,12 @@ pub struct Simulator {
#[derive(Clone)]
struct RegisterFile {
- registers: [u32; 32],
+ registers: [isa::Word; 32],
}
#[derive(Clone)]
struct Core {
- pc: usize,
+ pc: isa::Address,
registers: RegisterFile,
running: bool,
}
@@ -22,19 +22,19 @@ struct Core {
#[derive(Debug)]
enum Trap {
IllegalInstruction {
- address: usize,
+ address: isa::Address,
instruction: isa::Instruction,
},
IllegalRead {
- address: usize,
+ address: isa::Address,
instruction: isa::Instruction,
- memory_address: usize,
+ memory_address: isa::Address,
},
IllegalWrite {
- address: usize,
+ address: isa::Address,
instruction: isa::Instruction,
- memory_address: usize,
- memory_value: u32,
+ memory_address: isa::Address,
+ memory_value: isa::Word,
}
}
@@ -45,14 +45,14 @@ impl RegisterFile {
}
}
- fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: u32) {
+ fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: isa::Word) {
// TODO: should be safe to use unchecked index
let reg = reg.into();
if reg == isa::Register::X0 { return; }
self.registers[reg.as_num()] = value;
}
- fn read_word<T: Into<isa::Register>>(&mut self, reg: T) -> u32 {
+ fn read_word<T: Into<isa::Register>>(&mut self, reg: T) -> isa::Word {
self.registers[reg.into().as_num()]
}
}
@@ -73,7 +73,7 @@ impl Simulator {
registers: RegisterFile::new(),
running: true,
};
- let mut cores = vec![base_core ; self.num_cores];
+ let mut cores = vec![base_core; self.num_cores];
// hardcode GP
cores[0].registers.write_word(isa::Register::X3, 0x10860);
// hardcode SP
@@ -100,27 +100,56 @@ impl Simulator {
match inst.opcode() {
isa::opcodes::JALR => {
// TODO: assert funct3 is 0
- let target = ((core.registers.read_word(inst.rs1()) as i32) + inst.i_imm()) as u32;
+ let target = ((core.registers.read_word(inst.rs1()) as isa::SignedWord) + inst.i_imm()) as isa::Address;
if target == 0x0 {
// ret
core.running = false;
}
+ else {
+ let target = (((pc as isa::SignedWord) + inst.i_imm()) as isa::Address) & 0xFFFFFFFE;
+ core.registers.write_word(inst.rd(), (pc + 4) as isa::Word);
+ core.pc = target;
+ return;
+ }
},
isa::opcodes::JAL => {
-
+ let target = ((pc as isa::SignedWord) + inst.uj_imm()) as isa::Address;
+ core.registers.write_word(inst.rd(), (pc + 4) as isa::Word);
+ core.pc = target;
+ return;
}
isa::opcodes::BRANCH => {
-
+ let target = ((pc as isa::SignedWord) + inst.sb_imm()) as isa::Address;
+ let rs1 = core.registers.read_word(inst.rs1());
+ let rs2 = core.registers.read_word(inst.rs2());
+ if match inst.funct3() {
+ isa::funct3::BEQ => rs1 == rs2,
+ isa::funct3::BNE => rs1 != rs2,
+ isa::funct3::BLT => (rs1 as isa::SignedWord) < (rs2 as isa::SignedWord),
+ isa::funct3::BGE => (rs1 as isa::SignedWord) > (rs2 as isa::SignedWord),
+ isa::funct3::BLTU => rs1 < rs2,
+ isa::funct3::BGEU => rs1 > rs2,
+ _ => {
+ self.trap(core, Trap::IllegalInstruction {
+ address: pc,
+ instruction: inst,
+ });
+ false
+ }
+ } {
+ core.pc = target;
+ return;
+ }
},
isa::opcodes::INTEGER_IMMEDIATE => {
let imm = inst.i_imm();
- let src: i32 = core.registers.read_word(inst.rs1()) as i32;
+ let src = core.registers.read_word(inst.rs1()) as isa::SignedWord;
if let Some(value) = match inst.funct3() {
isa::funct3::ADDI => {
- Some(src.wrapping_add(imm) as u32)
+ Some(src.wrapping_add(imm) as isa::Word)
},
isa::funct3::SLLI => {
- Some((src << inst.shamt()) as u32)
+ Some((src << inst.shamt()) as isa::Word)
},
isa::funct3::SLTI => {
if src < imm {
@@ -131,7 +160,7 @@ impl Simulator {
}
},
isa::funct3::SLTIU => {
- if (src as u32) < (imm as u32) {
+ if (src as isa::Word) < (imm as isa::Word) {
Some(1)
}
else {
@@ -139,12 +168,12 @@ impl Simulator {
}
},
isa::funct3::XORI => {
- Some((src ^ imm) as u32)
+ Some((src ^ imm) as isa::Word)
},
isa::funct3::SRLI_SRAI => {
match inst.funct7() {
- isa::funct7::SRLI => Some(((src as u32) >> inst.shamt()) as u32),
- isa::funct7::SRAI => Some((src >> inst.shamt()) as u32),
+ isa::funct7::SRLI => Some(((src as isa::Word) >> inst.shamt()) as isa::Word),
+ isa::funct7::SRAI => Some((src >> inst.shamt()) as isa::Word),
_ => {
self.trap(core, Trap::IllegalInstruction {
address: pc,
@@ -155,10 +184,10 @@ impl Simulator {
}
},
isa::funct3::ORI => {
- Some((src | imm) as u32)
+ Some((src | imm) as isa::Word)
},
isa::funct3::ANDI => {
- Some((src & imm) as u32)
+ Some((src & imm) as isa::Word)
},
_ => {
self.trap(core, Trap::IllegalInstruction {
@@ -178,8 +207,8 @@ impl Simulator {
if let Some(value) = match inst.funct3() {
isa::funct3::ADD_SUB => {
match inst.funct7() {
- isa::funct7::ADD_SRL => Some(((src1 as i32).wrapping_add(src2 as i32)) as u32),
- isa::funct7::SUB_SRA => Some(((src1 as i32).wrapping_sub(src2 as i32)) as u32),
+ isa::funct7::ADD_SRL => Some(((src1 as isa::SignedWord).wrapping_add(src2 as isa::SignedWord)) as isa::Word),
+ isa::funct7::SUB_SRA => Some(((src1 as isa::SignedWord).wrapping_sub(src2 as isa::SignedWord)) as isa::Word),
_ => {
self.trap(core, Trap::IllegalInstruction {
address: pc,
@@ -193,7 +222,7 @@ impl Simulator {
Some(src1 << src2_shift)
},
isa::funct3::SLT => {
- if (src1 as i32) < (src2 as i32) {
+ if (src1 as isa::SignedWord) < (src2 as isa::SignedWord) {
Some(1)
}
else {
@@ -214,7 +243,7 @@ impl Simulator {
isa::funct3::SRL_SRA => {
match inst.funct7() {
isa::funct7::ADD_SRL => Some(src1 >> src2_shift),
- isa::funct7::SUB_SRA => Some(((src1 as i32) >> src2_shift) as u32),
+ isa::funct7::SUB_SRA => Some(((src1 as isa::SignedWord) >> src2_shift) as isa::Word),
_ => {
self.trap(core, Trap::IllegalInstruction {
address: pc,
@@ -245,7 +274,7 @@ impl Simulator {
isa::funct3::LW => {
let imm = inst.i_imm();
let base = core.registers.read_word(inst.rs1());
- let address = ((base as i32) + imm) as usize;
+ let address = ((base as isa::SignedWord) + imm) as isa::Address;
if let Some(value) = self.memory.read_word(address) {
core.registers.write_word(inst.rd(), value);
}
@@ -266,7 +295,7 @@ impl Simulator {
let imm = inst.s_imm();
let base = core.registers.read_word(inst.rs1());
let val = core.registers.read_word(inst.rs2());
- let address = ((base as i32) + imm) as usize;
+ let address = ((base as isa::SignedWord) + imm) as isa::Address;
self.memory.write_word(address, val);
}
_ => {