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-rw-r--r--src/memory.rs42
-rw-r--r--src/simulator.rs6
2 files changed, 45 insertions, 3 deletions
diff --git a/src/memory.rs b/src/memory.rs
index 052ffb7..958ef21 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -123,7 +123,23 @@ pub trait MemoryInterface {
}
}
+pub struct CacheMetadata {
+ /// How many sets are in the cache
+ pub num_sets: usize,
+ /// How many ways are in a set
+ pub num_ways: usize,
+ /// How many words are in a block/line
+ pub num_block_words: usize,
+ /// The tags currently in the cache, in order of set, then way
+ pub tags: Vec<Option<isa::Address>>,
+}
+
+pub trait CacheInterface : MemoryInterface {
+ fn cache_metadata(&self) -> CacheMetadata;
+}
+
pub type SharedMemory<'a> = Rc<RefCell<MemoryInterface + 'a>>;
+pub type SharedCache<'a> = Rc<RefCell<CacheInterface + 'a>>;
pub trait Mmu {
fn translate(&self, address: isa::Address) -> isa::Address;
@@ -441,3 +457,29 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> {
}
}
}
+
+impl<'a> CacheInterface for DirectMappedCache<'a> {
+ fn cache_metadata(&self) -> CacheMetadata {
+ let tags = {
+ let mut tags = Vec::new();
+
+ for set in self.cache.iter() {
+ if set.valid {
+ tags.push(Some(isa::Word(set.tag)));
+ }
+ else {
+ tags.push(None);
+ }
+ }
+
+ tags
+ };
+
+ CacheMetadata {
+ num_sets: self.num_sets as usize,
+ num_ways: 1,
+ num_block_words: self.block_words as usize,
+ tags: tags,
+ }
+ }
+}
diff --git a/src/simulator.rs b/src/simulator.rs
index 8e2a0a5..9071599 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -16,7 +16,7 @@
use isa;
use isa::IsaType;
-use memory::{MemoryInterface, MemoryError, Mmu, SharedMemory};
+use memory::{MemoryInterface, MemoryError, Mmu, SharedCache, SharedMemory};
use register_file::RegisterFile;
use syscall::SyscallHandler;
use trap::Trap;
@@ -27,7 +27,7 @@ pub struct Core<'a> {
registers: RegisterFile,
stall: u32,
running: bool,
- cache: SharedMemory<'a>,
+ cache: SharedCache<'a>,
mmu: Box<Mmu + 'a>,
cycle_count: u32,
stall_count: u32,
@@ -53,7 +53,7 @@ pub struct Simulator<'a, T: SyscallHandler> {
impl<'a> Core<'a> {
// TODO: take Rc<RefCell<>> to Memory as well?
pub fn new(id: usize, entry: isa::Address, sp: isa::Address,
- cache: SharedMemory<'a>, mmu: Box<Mmu + 'a>) -> Core<'a> {
+ cache: SharedCache<'a>, mmu: Box<Mmu + 'a>) -> Core<'a> {
let mut registers = RegisterFile::new();
registers.write_word(isa::Register::X2, sp);
Core {