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authorDavid Li <li.davidm96@gmail.com>2015-12-20 23:16:56 -0500
committerDavid Li <li.davidm96@gmail.com>2015-12-20 23:16:56 -0500
commit39ce6b062b6d36495098e39dfd813212757ac4f3 (patch)
tree1bb6a13b5934409793528bfb054d5243e52c9538 /src
parent600fcc814e27e7f38969726e1263a36592bbde58 (diff)
Fix immediate calculation in JAL
Diffstat (limited to 'src')
-rw-r--r--src/isa/mod.rs4
-rw-r--r--src/simulator.rs78
2 files changed, 42 insertions, 40 deletions
diff --git a/src/isa/mod.rs b/src/isa/mod.rs
index 6519a34..49fad10 100644
--- a/src/isa/mod.rs
+++ b/src/isa/mod.rs
@@ -146,7 +146,7 @@ impl Instruction {
let low11 = (self.word >> 20) & 0x1;
let low12 = (self.word >> 12) & 0xFF;
// Want sign-extension
- let low20 = (((self.word as SignedWord) >> 30) & 0x1) as Word;
+ let low20 = ((self.word as SignedWord) >> 30) as Word;
((low20 << 20) | (low12 << 12) | (low11 << 11) | (low1 << 1)) as SignedWord
}
@@ -154,7 +154,7 @@ impl Instruction {
let low1 = (self.word >> 8) & 0xF;
let low5 = (self.word >> 25) & 0x3F;
let low11 = (self.word >> 7) & 0x1;
- let low12 = (((self.word as SignedWord) >> 31) & 0x1) as Word;
+ let low12 = ((self.word as SignedWord) >> 31) as Word;
((low12 << 12) | (low11 << 11) | (low5 << 5) | (low1 << 1)) as SignedWord
}
}
diff --git a/src/simulator.rs b/src/simulator.rs
index d30ae7c..bc4443c 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -98,49 +98,50 @@ impl Simulator {
let pc = core.pc;
if let Some(inst) = self.memory.read_instruction(pc) {
match inst.opcode() {
- isa::opcodes::JALR => {
- // TODO: assert funct3 is 0
- let target = ((core.registers.read_word(inst.rs1()) as isa::SignedWord) + inst.i_imm()) as isa::Address;
- if target == 0x0 {
- // ret
- core.running = false;
- }
- else {
- let target = (((pc as isa::SignedWord) + inst.i_imm()) as isa::Address) & 0xFFFFFFFE;
- core.registers.write_word(inst.rd(), (pc + 4) as isa::Word);
- core.pc = target;
- return;
- }
- },
+ // isa::opcodes::JALR => {
+ // // TODO: assert funct3 is 0
+ // let target = ((core.registers.read_word(inst.rs1()) as isa::SignedWord) + inst.i_imm()) as isa::Address;
+ // if target == 0x0 {
+ // // ret
+ // core.running = false;
+ // }
+ // else {
+ // let target = (((pc as isa::SignedWord) + inst.i_imm()) as isa::Address) & 0xFFFFFFFE;
+ // core.registers.write_word(inst.rd(), (pc + 4) as isa::Word);
+ // core.pc = target;
+ // return;
+ // }
+ // },
isa::opcodes::JAL => {
let target = ((pc as isa::SignedWord) + inst.uj_imm()) as isa::Address;
core.registers.write_word(inst.rd(), (pc + 4) as isa::Word);
core.pc = target;
+ // panic!("JAL to {:X} 0x{:X}", pc, target);
return;
}
- isa::opcodes::BRANCH => {
- let target = ((pc as isa::SignedWord) + inst.sb_imm()) as isa::Address;
- let rs1 = core.registers.read_word(inst.rs1());
- let rs2 = core.registers.read_word(inst.rs2());
- if match inst.funct3() {
- isa::funct3::BEQ => rs1 == rs2,
- isa::funct3::BNE => rs1 != rs2,
- isa::funct3::BLT => (rs1 as isa::SignedWord) < (rs2 as isa::SignedWord),
- isa::funct3::BGE => (rs1 as isa::SignedWord) > (rs2 as isa::SignedWord),
- isa::funct3::BLTU => rs1 < rs2,
- isa::funct3::BGEU => rs1 > rs2,
- _ => {
- self.trap(core, Trap::IllegalInstruction {
- address: pc,
- instruction: inst,
- });
- false
- }
- } {
- core.pc = target;
- return;
- }
- },
+ // isa::opcodes::BRANCH => {
+ // let target = ((pc as isa::SignedWord) + inst.sb_imm()) as isa::Address;
+ // let rs1 = core.registers.read_word(inst.rs1());
+ // let rs2 = core.registers.read_word(inst.rs2());
+ // if match inst.funct3() {
+ // isa::funct3::BEQ => rs1 == rs2,
+ // isa::funct3::BNE => rs1 != rs2,
+ // isa::funct3::BLT => (rs1 as isa::SignedWord) < (rs2 as isa::SignedWord),
+ // isa::funct3::BGE => (rs1 as isa::SignedWord) > (rs2 as isa::SignedWord),
+ // isa::funct3::BLTU => rs1 < rs2,
+ // isa::funct3::BGEU => rs1 > rs2,
+ // _ => {
+ // self.trap(core, Trap::IllegalInstruction {
+ // address: pc,
+ // instruction: inst,
+ // });
+ // false
+ // }
+ // } {
+ // core.pc = target;
+ // return;
+ // }
+ // },
isa::opcodes::INTEGER_IMMEDIATE => {
let imm = inst.i_imm();
let src = core.registers.read_word(inst.rs1()) as isa::SignedWord;
@@ -306,7 +307,8 @@ impl Simulator {
0x0 => {
// System call
println!("System call {}:", core.registers.read_word(isa::Register::X10));
- println!("Argument {:X}:", core.registers.read_word(isa::Register::X11));
+ let address = core.registers.read_word(isa::Register::X11) as usize;
+ println!("Argument {:X}: {:?}", address, self.memory.read_word(address));
}
_ => {