diff options
author | David Li <li.davidm96@gmail.com> | 2016-01-09 15:34:14 -0700 |
---|---|---|
committer | David Li <li.davidm96@gmail.com> | 2016-01-09 15:34:14 -0700 |
commit | f2591ea1714703d1f9c3c50ab6e4c0da74c584ba (patch) | |
tree | 4344d213935438d94dd61aecc621ecf6e97ac952 /src | |
parent | 02e28802676127d1ee71f9a751a0da8f0890204b (diff) |
Step caches separately from cores
Diffstat (limited to 'src')
-rw-r--r-- | src/simulator.rs | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/simulator.rs b/src/simulator.rs index f675e58..716c0e1 100644 --- a/src/simulator.rs +++ b/src/simulator.rs @@ -361,12 +361,14 @@ impl<'a> Core<'a> { } impl<'a, T: SyscallHandler> Simulator<'a, T> { - pub fn new(cores: Vec<Core<'a>>, memory: SharedMemory<'a>, syscall: T) + pub fn new(cores: Vec<Core<'a>>, memory: SharedMemory<'a>, + caches: Vec<SharedMemory<'a>>, syscall: T) -> Simulator<'a, T> { // TODO: initialize GP, registers (GP is in headers) Simulator { cores: cores, memory: memory, + caches: caches, syscall: syscall, } } @@ -389,10 +391,13 @@ impl<'a, T: SyscallHandler> Simulator<'a, T> { // TODO: trap } - core.cache.borrow_mut().step(); ran = true; } + for cache in self.caches.iter() { + cache.borrow_mut().step(); + } + ran } |