From f2591ea1714703d1f9c3c50ab6e4c0da74c584ba Mon Sep 17 00:00:00 2001 From: David Li Date: Sat, 9 Jan 2016 15:34:14 -0700 Subject: Step caches separately from cores --- src/simulator.rs | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/simulator.rs b/src/simulator.rs index f675e58..716c0e1 100644 --- a/src/simulator.rs +++ b/src/simulator.rs @@ -361,12 +361,14 @@ impl<'a> Core<'a> { } impl<'a, T: SyscallHandler> Simulator<'a, T> { - pub fn new(cores: Vec>, memory: SharedMemory<'a>, syscall: T) + pub fn new(cores: Vec>, memory: SharedMemory<'a>, + caches: Vec>, syscall: T) -> Simulator<'a, T> { // TODO: initialize GP, registers (GP is in headers) Simulator { cores: cores, memory: memory, + caches: caches, syscall: syscall, } } @@ -389,10 +391,13 @@ impl<'a, T: SyscallHandler> Simulator<'a, T> { // TODO: trap } - core.cache.borrow_mut().step(); ran = true; } + for cache in self.caches.iter() { + cache.borrow_mut().step(); + } + ran } -- cgit v1.2.3