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authorDavid Li <li.davidm96@gmail.com>2015-12-15 13:38:54 -0500
committerDavid Li <li.davidm96@gmail.com>2015-12-15 13:38:58 -0500
commit32b7dacc64b70c12096ecb4007465e41f3c2098a (patch)
tree91e1e1d3a11351c92ae8591d3fcac5d8361c7af1 /src/simulator.rs
Outline the simulator
Diffstat (limited to 'src/simulator.rs')
-rw-r--r--src/simulator.rs58
1 files changed, 58 insertions, 0 deletions
diff --git a/src/simulator.rs b/src/simulator.rs
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+++ b/src/simulator.rs
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+use isa;
+use binary::{Binary};
+use memory::{Memory};
+
+pub struct Simulator<'a> {
+ binary: Binary<'a>,
+ num_cores: usize,
+ memory: Memory,
+}
+
+#[derive(Clone)]
+struct Core {
+ pc: usize,
+}
+
+struct RegisterFile {
+ registers: [u32; 32],
+}
+
+impl<'a> Simulator<'a> {
+ pub fn new(num_cores: usize, binary: Binary<'a>) -> Simulator<'a> {
+ Simulator {
+ binary: binary,
+ num_cores: num_cores,
+ memory: Memory::new(0x20000),
+ }
+ }
+
+ pub fn run(&mut self) {
+ let mut cores = vec![Core { pc: 0x10000, }; self.num_cores];
+ // TODO: set up memory, cache, devices
+ // TODO: map binary into RAM
+ loop {
+ for core in cores.iter_mut() {
+ self.step_core(core);
+ }
+ }
+ }
+
+ fn step_core(&mut self, core: &mut Core) {
+ if let Some(inst) = self.memory.read_instruction(core.pc) {
+ match inst.opcode() {
+ isa::opcodes::Branch => {
+
+ }
+ isa::opcodes::IntegerImmediate => {
+
+ }
+ _ => {
+
+ }
+ }
+ }
+ else {
+ // trap
+ }
+ }
+}