From 32b7dacc64b70c12096ecb4007465e41f3c2098a Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Tue, 15 Dec 2015 13:38:54 -0500
Subject: Outline the simulator

---
 src/simulator.rs | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 src/simulator.rs

(limited to 'src/simulator.rs')

diff --git a/src/simulator.rs b/src/simulator.rs
new file mode 100644
index 0000000..e965686
--- /dev/null
+++ b/src/simulator.rs
@@ -0,0 +1,58 @@
+use isa;
+use binary::{Binary};
+use memory::{Memory};
+
+pub struct Simulator<'a> {
+    binary: Binary<'a>,
+    num_cores: usize,
+    memory: Memory,
+}
+
+#[derive(Clone)]
+struct Core {
+    pc: usize,
+}
+
+struct RegisterFile {
+    registers: [u32; 32],
+}
+
+impl<'a> Simulator<'a> {
+    pub fn new(num_cores: usize, binary: Binary<'a>) -> Simulator<'a> {
+        Simulator {
+            binary: binary,
+            num_cores: num_cores,
+            memory: Memory::new(0x20000),
+        }
+    }
+
+    pub fn run(&mut self) {
+        let mut cores = vec![Core { pc: 0x10000, }; self.num_cores];
+        // TODO: set up memory, cache, devices
+        // TODO: map binary into RAM
+        loop {
+            for core in cores.iter_mut() {
+                self.step_core(core);
+            }
+        }
+    }
+
+    fn step_core(&mut self, core: &mut Core) {
+        if let Some(inst) = self.memory.read_instruction(core.pc) {
+            match inst.opcode() {
+                isa::opcodes::Branch => {
+                    
+                }
+                isa::opcodes::IntegerImmediate => {
+                    
+                }
+                _ => {
+                    
+                }
+            }
+        }
+        else {
+            // trap
+        }
+    }
+}
-- 
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