aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDavid Li <li.davidm96@gmail.com>2016-01-06 10:51:37 -0700
committerDavid Li <li.davidm96@gmail.com>2016-01-06 10:51:37 -0700
commitb7111860f29bb123365794a8cdabbbf473463204 (patch)
treed6533127bcacd74b2fbe90874bede83f90fcb33f
parente6d2693a836788894373af1b35ed678b3561f6ac (diff)
Get rid of Box in memory refs
-rw-r--r--src/lib.rs11
-rw-r--r--src/memory.rs2
-rw-r--r--src/simulator.rs63
3 files changed, 44 insertions, 32 deletions
diff --git a/src/lib.rs b/src/lib.rs
index 8bad489..475b357 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -62,11 +62,9 @@ fn test_elfloader() {
memory.write_segment(&mmu2, text, text_offset as usize);
memory.write_segment(&mmu2, data, data_offset as usize);
- let memory_box = Box::new(memory) as Box<memory::MemoryInterface>;
- let memory_ref = Rc::new(RefCell::new(memory_box));
+ let memory_ref = Rc::new(RefCell::new(memory));
let cache = memory::DirectMappedCache::new(4, 4, memory_ref.clone());
- let cache_box = Box::new(cache) as Box<memory::MemoryInterface>;
- let cache_ref = Rc::new(RefCell::new(cache_box));
+ let cache_ref = Rc::new(RefCell::new(cache));
let core = simulator::Core::new(
start, 0x1000,
cache_ref.clone(), Box::new(mmu));
@@ -87,7 +85,7 @@ mod tests {
use std::cell::RefCell;
let memory = Memory::new(16);
- let memory_ref = Rc::new(RefCell::new(Box::new(memory) as Box<MemoryInterface>));
+ let memory_ref = Rc::new(RefCell::new(memory));
let dm_cache_word = DirectMappedCache::new(4, 1, memory_ref.clone());
let dm_cache_doubleword = DirectMappedCache::new(4, 2, memory_ref.clone());
@@ -134,8 +132,7 @@ mod tests {
stall_cycles: memory.latency(),
});
- let memory_box = Box::new(memory) as Box<MemoryInterface>;
- let memory_ref = Rc::new(RefCell::new(memory_box));
+ let memory_ref = Rc::new(RefCell::new(memory));
let mut dm_cache = DirectMappedCache::new(4, 4, memory_ref.clone());
assert_eq!(dm_cache.read_word(0x10), stall);
diff --git a/src/memory.rs b/src/memory.rs
index 2e59ff1..226b6c2 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -89,7 +89,7 @@ pub trait MemoryInterface {
}
}
-pub type SharedMemory<'a> = Rc<RefCell<Box<MemoryInterface + 'a>>>;
+pub type SharedMemory<'a> = Rc<RefCell<MemoryInterface + 'a>>;
pub trait Mmu {
fn translate(&self, address: isa::Address) -> isa::Address;
diff --git a/src/simulator.rs b/src/simulator.rs
index 0101c44..4feb1c0 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -368,34 +368,49 @@ impl<'a> Simulator<'a> {
}
}
- pub fn run(&mut self) {
- loop {
- let mut ran = false;
- for core in self.cores.iter_mut() {
- if !core.running {
- continue;
- }
+ fn step(&mut self) -> bool {
+ let mut ran = false;
+ for core in self.cores.iter_mut() {
+ if !core.running {
+ continue;
+ }
- let pc = core.pc;
- let pc = core.mmu.translate(pc);
- let inst = self.memory.borrow_mut().read_instruction(pc);
+ let pc = core.pc;
+ let pc = core.mmu.translate(pc);
+ let inst = self.memory.borrow_mut().read_instruction(pc);
- if let Some(inst) = inst {
- core.step(inst);
- }
- else {
- // TODO: trap
- }
+ if let Some(inst) = inst {
+ core.step(inst);
+ }
+ else {
+ // TODO: trap
+ }
- core.cache.borrow_mut().step();
- ran = true;
+ core.cache.borrow_mut().step();
+ ran = true;
+ }
+ if !ran {
+ println!("All cores are not running, stopping...");
+ for (i, core) in self.cores.iter().enumerate() {
+ println!("Core {}: stalled {} of {}", i, core.stall_count, core.cycle_count);
}
- if !ran {
- println!("All cores are not running, stopping...");
- for (i, core) in self.cores.iter().enumerate() {
- println!("Core {}: stalled {} of {}", i, core.stall_count, core.cycle_count);
- }
- break;
+ }
+
+ ran
+ }
+
+ pub fn run(&mut self) {
+ loop {
+ if !self.step() {
+ break
+ }
+ }
+ }
+
+ pub fn run_max(&mut self, cycles: usize) {
+ for _ in 0..cycles {
+ if !self.step() {
+ break
}
}
}