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rustv
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A minimal, intentionally inaccurate RISC-V ISA simulator in Rust
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master
chore(Changelog): add clog config
David Li
10 years
Tag
Download
Author
Age
0.5.1
commit bf95ae676d...
David Li
10 years
0.5.0
commit 657d1fb5aa...
David Li
10 years
0.4.1
commit 4a56b90b38...
David Li
10 years
0.2.5
commit 7a3dae00d7...
David Li
10 years
Age
Commit message
Author
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2016-01-25
chore(Changelog): add clog config
HEAD
master
David Li
1
-0
/
+8
2016-01-25
chore(Changelog): add changelog (generated with clog)
David Li
1
-0
/
+10
2016-01-25
feat(cache): add callback for requesting new block
David Li
2
-0
/
+4
2016-01-24
Get rid of redundant 'Cache' in names
David Li
2
-13
/
+13
2016-01-24
Provide API to react to cache events
David Li
4
-243
/
+301
2016-01-17
Distinguish between memory and cache at type level
David Li
2
-3
/
+45
2016-01-16
Bump version to 0.5.1
0.5.1
David Li
1
-1
/
+1
2016-01-16
Have simulator return reason for halting
David Li
2
-14
/
+29
2016-01-15
Bump version to 0.5.0
0.5.0
David Li
1
-1
/
+1
2016-01-15
Allow stalls that do not retry instruction
David Li
4
-7
/
+18
[...]
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https://git.lidavidm.me/rustv