diff options
| -rw-r--r-- | TODO.md | 1 | ||||
| -rw-r--r-- | src/main.rs | 13 | ||||
| -rw-r--r-- | src/shareable_cache.rs | 26 |
3 files changed, 25 insertions, 15 deletions
@@ -19,6 +19,7 @@ https://git.lidavidm.me/cacheracer/. - [ ] Make sure `ReverseMmu` maps addresses correctly (i.e. 0x0 should map to an actual array element) +- [ ] Sneak attack/retreat needs to be per-core - [ ] Implement global data structures - [ ] Player status - [ ] Core status diff --git a/src/main.rs b/src/main.rs index c7ee66f..2f607a6 100644 --- a/src/main.rs +++ b/src/main.rs @@ -87,17 +87,25 @@ fn main() { let cache2_ref = Rc::new(RefCell::new(cache2)); let (cache1, cache2) = ShareableCache::new(cache_ref.clone(), cache2_ref.clone()); + let mut core_caches = vec![]; let mut cores = vec![]; for i in 0..4 { + let c1 = Rc::new(RefCell::new(cache1.clone())); + core_caches.push(c1.clone()); let mut core = simulator::Core::new( - i, start1, (0x100000 * (i + 1)) as u32, cache1.clone(), + i, start1, (0x100000 * (i + 1)) as u32, c1, Box::new(memory::IdentityMmu::new()) ); core.registers().write_word(isa::Register::X10, i as isa::Word); cores.push(core); + } + + for i in 4..8 { + let c2 = Rc::new(RefCell::new(cache2.clone())); + core_caches.push(c2.clone()); let mut core = simulator::Core::new( - i, start2, (0x100000 * (i + 1)) as u32, cache2.clone(), + i, start2, (0x100000 * (i + 1)) as u32, c2, Box::new(memory::ReverseMmu::new(0x4000000)) ); core.registers().write_word(isa::Register::X10, i as isa::Word); @@ -105,7 +113,6 @@ fn main() { } let steppable_caches = vec![cache_ref.clone() as memory::SharedMemory, cache2_ref]; - let core_caches = vec![cache1, cache2]; let system = SyscallHandler::new(memory_ref.clone(), core_caches); let mut simulator = simulator::Simulator::new( cores, memory_ref.clone(), steppable_caches, system); diff --git a/src/shareable_cache.rs b/src/shareable_cache.rs index a8fee51..09d514f 100644 --- a/src/shareable_cache.rs +++ b/src/shareable_cache.rs @@ -1,6 +1,3 @@ -use std::cell::RefCell; -use std::rc::Rc; - use rustv::isa; use rustv::memory::{MemoryInterface, Result, SharedMemory}; @@ -8,8 +5,6 @@ use rustv::memory::{MemoryInterface, Result, SharedMemory}; /// set-associative cache. #[derive(Clone)] pub struct ShareableCache<'a> { - // The idea is to create two separate ShareableCaches, one for - // each player. primary: SharedMemory<'a>, secondary: SharedMemory<'a>, secondary_enabled: bool, @@ -18,19 +13,19 @@ pub struct ShareableCache<'a> { impl<'a> ShareableCache<'a> { pub fn new(cache1: SharedMemory<'a>, cache2: SharedMemory<'a>) - -> (Rc<RefCell<ShareableCache<'a>>>, - Rc<RefCell<ShareableCache<'a>>>) { - (Rc::new(RefCell::new(ShareableCache { + -> (ShareableCache<'a>, + ShareableCache<'a>) { + (ShareableCache { primary: cache1.clone(), secondary: cache2.clone(), secondary_enabled: false, use_secondary: false, - })), Rc::new(RefCell::new(ShareableCache { + }, ShareableCache { primary: cache2.clone(), secondary: cache1.clone(), secondary_enabled: false, use_secondary: false, - }))) + }) } pub fn enable_secondary(&mut self) { @@ -86,10 +81,17 @@ impl<'a> MemoryInterface for ShareableCache<'a> { fn write_word(&mut self, address: isa::Address, value: isa::Word) -> Result<()> { if self.secondary_enabled { - if self.primary.borrow().is_address_accessible(address) { + let primary_accessible = { + self.primary.borrow().is_address_accessible(address) + }; + let secondary_accessible = { + self.secondary.borrow().is_address_accessible(address) + }; + + if primary_accessible { self.primary.borrow_mut().write_word(address, value) } - else if self.secondary.borrow().is_address_accessible(address) { + else if secondary_accessible { self.secondary.borrow_mut().write_word(address, value) } else { |