Update rustv version

1 files changed, 27 insertions, 15 deletions

diff --git a/src/main.rs b/src/main.rs
index 50cc8ee..1745084 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -21,6 +21,7 @@ use rustv::memory::Mmu;
 use rustv::simulator;
 
 use memory_tracker::MemoryTracker;
+use shareable_cache::ShareableCache;
 use system::SyscallHandler;
 
 const USAGE: &'static str = "
@@ -40,8 +41,6 @@ struct Args {
     arg_program2: String,
 }
 
-
-
 fn load_program<T: memory::Mmu>(memory: &mut memory::Memory,
                                 mmu: &T, path: &str) -> isa::Address {
     let mut f = File::open(path).unwrap();
@@ -70,7 +69,7 @@ fn main() {
     let mmu = memory::IdentityMmu::new();
     // TODO: account for word-vs-byte addressed. Use newtype pattern?
     let mmu2 = memory::ReverseMmu::new(0x4000000);
-    let mut memory = memory::Memory::new(0x400000);
+    let mut memory = memory::Memory::new(0x1000000);
 
     let start1 = load_program(&mut memory, &mmu, &args.arg_program1);
     let start2 = load_program(&mut memory, &mmu2, &args.arg_program2);
@@ -78,24 +77,37 @@ fn main() {
     let memory = MemoryTracker::new(memory, 0x43, 0x42);
 
     let memory_ref = Rc::new(RefCell::new(memory));
-    let cache = memory::DirectMappedCache::new(4, 64, memory_ref.clone());
+    let cache = memory::DirectMappedCache::new(2, 64, memory_ref.clone());
     let cache_ref = Rc::new(RefCell::new(cache));
-    let cache2 = memory::DirectMappedCache::new(4, 64, memory_ref.clone());
+    let cache2 = memory::DirectMappedCache::new(2, 64, memory_ref.clone());
     let cache2_ref = Rc::new(RefCell::new(cache2));
 
-    let core = simulator::Core::new(
-        start1, 0x1000,
-        cache_ref.clone(), Box::new(mmu));
-    let core2 = simulator::Core::new(
-        start2, 0x1000,
-        cache2_ref.clone(), Box::new(mmu2));
-    let cores = vec![core, core2];
-    let system = SyscallHandler::new(memory_ref.clone());
+    let (cache1, cache2) = ShareableCache::new(cache_ref.clone(), cache2_ref.clone());
+
+    let mut cores = vec![];
+    for i in 0..4 {
+        let mut core = simulator::Core::new(
+            i, start1, (0x1000 + i * 0x1000) as u32, cache1.clone(),
+            Box::new(memory::IdentityMmu::new())
+            );
+        core.registers().write_word(isa::Register::X10, i as isa::Word);
+        cores.push(core);
+        let mut core = simulator::Core::new(
+            i, start2, (0x1000 + i * 0x1000) as u32, cache2.clone(),
+            Box::new(memory::ReverseMmu::new(0x4000000))
+            );
+        core.registers().write_word(isa::Register::X10, i as isa::Word);
+        cores.push(core);
+    }
+
+    let steppable_caches = vec![cache_ref.clone() as memory::SharedMemory, cache2_ref];
+    let core_caches = vec![cache1, cache2];
+    let system = SyscallHandler::new(memory_ref.clone(), core_caches);
     let mut simulator = simulator::Simulator::new(
-        cores, memory_ref.clone(), system);
+        cores, memory_ref.clone(), steppable_caches, system);
 
     // let cycles = 0x1000000;
-    let cycles = 0x1000000;
+    let cycles = 0x50000;
     let start = time::precise_time_s();
     simulator.run_max(cycles);
     let end = time::precise_time_s();