1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
use isa;
use binary::{Binary};
use memory::{Memory};
pub struct Simulator {
num_cores: usize,
memory: Memory,
}
#[derive(Clone)]
struct Core {
pc: usize,
}
struct RegisterFile {
registers: [u32; 32],
}
impl RegisterFile {
fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: u32) {
// TODO: should be safe to use unchecked index
self.registers[reg.into().as_num()] = value;
}
}
impl Simulator {
pub fn new(num_cores: usize, binary: Binary) -> Simulator {
let memory = Memory::new(0x2000, binary);
// TODO: initialize GP, registers (GP is in headers)
Simulator {
num_cores: num_cores,
memory: memory,
}
}
pub fn run(&mut self) {
let mut cores = vec![Core { pc: 0x10000, }; self.num_cores];
loop {
for core in cores.iter_mut() {
self.step_core(core);
}
}
}
fn step_core(&mut self, core: &mut Core) {
if let Some(inst) = self.memory.read_instruction(core.pc) {
match inst.opcode() {
isa::opcodes::BRANCH => {
},
isa::opcodes::INTEGER_IMMEDIATE => match inst.funct3() {
isa::funct3::ADDI => {
println!("ADDI");
}
_ => {
panic!("Invalid integer-immediate funct3code: 0x{:x}", inst.funct3());
}
},
isa::opcodes::LOAD => match inst.funct3() {
isa::funct3::LW => {
println!("LW");
}
_ => {
panic!("Invalid load funct3code: 0x{:x}", inst.funct3());
}
},
isa::opcodes::STORE => match inst.funct3() {
isa::funct3::SW => {
println!("SW");
}
_ => {
panic!("Invalid store funct3code: 0x{:x}", inst.funct3());
}
},
_ => {
panic!("Invalid opcode: 0x{:02X}", inst.opcode());
}
}
}
else {
// trap
}
core.pc += 4;
}
}
|
