1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
|
use isa::{self, Instruction};
use binary::{Binary};
pub struct Memory {
memory: Vec<u32>,
}
#[derive(Clone)]
struct CacheBlock {
valid: bool,
tag: u32,
contents: Vec<u32>,
}
// TODO: probably want different caches for different strategies, and
// investigate how LRU is implemented
// TODO: use hashtable for a way?
// TODO: hashtable-based FA cache?
pub struct Cache {
num_sets: usize,
num_ways: usize,
block_words: usize,
cache: Vec<Vec<CacheBlock>>,
}
// TODO: refactor impls into a MemoryController(?) trait
impl Memory {
pub fn new(size: isa::Address, binary: Binary) -> Memory {
let mut memory = binary.words.clone();
if size > memory.len() {
let remainder = size - memory.len();
memory.reserve(remainder);
}
Memory {
memory: memory,
}
}
pub fn read_word(&self, address: isa::Address) -> Option<isa::Word> {
// memory is word-addressed but addresses are byte-addressed
self.memory.get(address / 4).map(Clone::clone)
}
pub fn write_word(&mut self, address: isa::Address, value: isa::Word) -> Option<()> {
let address = address / 4;
if address >= self.memory.len() {
None
}
else {
self.memory[address] = value;
Some(())
}
}
pub fn read_instruction(&self, pc: isa::Address) -> Option<Instruction> {
self.memory.get(pc / 4).map(Clone::clone).map(Instruction::new)
}
}
impl Cache {
pub fn new(sets: usize, ways: usize, block_words: usize) -> Cache {
Cache {
num_sets: sets,
num_ways: ways,
block_words: block_words,
cache: vec![vec![CacheBlock {
valid: false,
tag: 0,
contents: vec![0; block_words],
}; ways]; sets],
}
}
fn read_word(&self, address: isa::Address) -> Option<isa::Word> {
None
}
fn write_word(&mut self, address: isa::Address, value: isa::Word) -> Option<()> {
None
}
fn invalidate(&mut self, address: isa::Address) {
}
}
|
