From 9b37e5da43f7e2a0e42bc36c0a1b1cc66a402808 Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Wed, 6 Jan 2016 15:37:08 -0700
Subject: Implement LUI, AUIPC

---
 src/isa/mod.rs     | 4 ++++
 src/isa/opcodes.rs | 2 ++
 src/simulator.rs   | 7 +++++++
 3 files changed, 13 insertions(+)

(limited to 'src')

diff --git a/src/isa/mod.rs b/src/isa/mod.rs
index 9da1751..8a6e65b 100644
--- a/src/isa/mod.rs
+++ b/src/isa/mod.rs
@@ -176,4 +176,8 @@ impl Instruction {
         let low12 = ((self.word as SignedWord) >> 31) as Word;
         ((low12 << 12) | (low11 << 11) | (low5 << 5) | (low1 << 1)) as SignedWord
     }
+
+    pub fn u_imm(&self) -> SignedWord {
+        (self.word & 0xFFFFF000) as SignedWord
+    }
 }
diff --git a/src/isa/opcodes.rs b/src/isa/opcodes.rs
index 39401cd..8ca715e 100644
--- a/src/isa/opcodes.rs
+++ b/src/isa/opcodes.rs
@@ -14,6 +14,8 @@
 // You should have received a copy of the GNU General Public License
 // along with rustv.  If not, see <http://www.gnu.org/licenses/>.
 
+pub const LUI: u32 = 0x37;
+pub const AUIPC: u32 = 0x17;
 pub const BRANCH: u32 = 0x63;
 pub const JALR: u32 = 0x67;
 pub const JAL: u32 = 0x6F;
diff --git a/src/simulator.rs b/src/simulator.rs
index 006244a..073de67 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -105,6 +105,13 @@ impl<'a> Core<'a> {
         }
 
         match inst.opcode() {
+            isa::opcodes::LUI => {
+                self.registers.write_word(inst.rd(), inst.u_imm() as isa::Word)
+            },
+            isa::opcodes::AUIPC => {
+                let result = (pc as isa::SignedWord) + inst.u_imm();
+                self.registers.write_word(inst.rd(), result as isa::Word);
+            },
             isa::opcodes::JALR => {
                 // TODO: assert funct3 is 0
                 let base = self.registers.read_word(inst.rs1())
-- 
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