From 9888788cd4894c0c00f7373fc0cd6915941d638d Mon Sep 17 00:00:00 2001 From: David Li Date: Sun, 20 Dec 2015 15:14:52 -0500 Subject: Implement logic for RV32I branch instructions --- src/isa/funct3.rs | 7 +++++++ src/simulator.rs | 22 +++++++++++++++++++++- 2 files changed, 28 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/isa/funct3.rs b/src/isa/funct3.rs index be2eafa..e74da96 100644 --- a/src/isa/funct3.rs +++ b/src/isa/funct3.rs @@ -16,6 +16,13 @@ pub const SRL_SRA: u32 = 0x5; pub const OR: u32 = 0x6; pub const AND: u32 = 0x7; +pub const BEQ: u32 = 0b000; +pub const BNE: u32 = 0b001; +pub const BLT: u32 = 0b100; +pub const BGE: u32 = 0b101; +pub const BLTU: u32 = 0b110; +pub const BGEU: u32 = 0b111; + pub const LW: u32 = 0x2; pub const SW: u32 = 0x2; diff --git a/src/simulator.rs b/src/simulator.rs index bf39c5e..3ca11d9 100644 --- a/src/simulator.rs +++ b/src/simulator.rs @@ -120,7 +120,27 @@ impl Simulator { return; } isa::opcodes::BRANCH => { - + let target = ((pc as i32) + inst.sb_imm()) as usize; + let rs1 = core.registers.read_word(inst.rs1()); + let rs2 = core.registers.read_word(inst.rs2()); + if match inst.funct3() { + isa::funct3::BEQ => rs1 == rs2, + isa::funct3::BNE => rs1 != rs2, + isa::funct3::BLT => (rs1 as i32) < (rs2 as i32), + isa::funct3::BGE => (rs1 as i32) > (rs2 as i32), + isa::funct3::BLTU => rs1 < rs2, + isa::funct3::BGEU => rs1 > rs2, + _ => { + self.trap(core, Trap::IllegalInstruction { + address: pc, + instruction: inst, + }); + false + } + } { + core.pc = target; + return; + } }, isa::opcodes::INTEGER_IMMEDIATE => { let imm = inst.i_imm(); -- cgit v1.2.3