From 36b21d7691bb452a68d857a71c16b9f922b047a2 Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Wed, 13 Jan 2016 09:25:57 -0700
Subject: Pass MMU to syscall handler

---
 src/simulator.rs | 4 +++-
 src/syscall.rs   | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/simulator.rs b/src/simulator.rs
index 1c87d57..d625347 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -338,7 +338,9 @@ impl<'a> Core<'a> {
             },
             isa::opcodes::SYSTEM => match inst.i_imm() {
                 0x0 => {
-                    if let Some(trap) = system.syscall(self.id, &mut self.registers) {
+                    let result = system.syscall(self.id, &mut self.registers,
+                                                &*self.mmu);
+                    if let Some(trap) = result {
                         self.trap(trap);
                     }
                 }
diff --git a/src/syscall.rs b/src/syscall.rs
index 4620e5f..6da9e47 100644
--- a/src/syscall.rs
+++ b/src/syscall.rs
@@ -14,10 +14,12 @@
 // You should have received a copy of the GNU General Public License
 // along with rustv.  If not, see <http://www.gnu.org/licenses/>.
 
+use memory::Mmu;
 use register_file::RegisterFile;
 use trap;
 
 pub trait SyscallHandler {
     // Can't take cache because syscall can't stall
-    fn syscall(&mut self, core_id: usize, registers: &mut RegisterFile) -> Option<trap::Trap>;
+    fn syscall(&mut self, core_id: usize,
+               registers: &mut RegisterFile, mmu: &Mmu) -> Option<trap::Trap>;
 }
-- 
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