From 32b7dacc64b70c12096ecb4007465e41f3c2098a Mon Sep 17 00:00:00 2001 From: David Li Date: Tue, 15 Dec 2015 13:38:54 -0500 Subject: Outline the simulator --- src/binary.rs | 15 ++++++++++++++ src/cache.rs | 8 ++++++++ src/isa/mod.rs | 32 ++++++++++++++++++++++++++++++ src/isa/opcodes.rs | 2 ++ src/lib.rs | 9 +++++++++ src/memory.rs | 21 ++++++++++++++++++++ src/simulator.rs | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 145 insertions(+) create mode 100644 src/binary.rs create mode 100644 src/cache.rs create mode 100644 src/isa/mod.rs create mode 100644 src/isa/opcodes.rs create mode 100644 src/lib.rs create mode 100644 src/memory.rs create mode 100644 src/simulator.rs (limited to 'src') diff --git a/src/binary.rs b/src/binary.rs new file mode 100644 index 0000000..2564637 --- /dev/null +++ b/src/binary.rs @@ -0,0 +1,15 @@ +pub struct Binary<'a> { + words: &'a [u32], +} + +impl<'a> Binary<'a> { + pub fn new(words: &'a [u32]) -> Binary<'a> { + Binary { + words: words, + } + } + + // pub fn new_from_hex_file() -> Binary<'a> { + + // } +} diff --git a/src/cache.rs b/src/cache.rs new file mode 100644 index 0000000..26fdc18 --- /dev/null +++ b/src/cache.rs @@ -0,0 +1,8 @@ +// pub struct Cache { +// } + +// impl Cache { +// pub fn new(sets: usize, ways: usize, block_size: usize) -> Cache { + +// } +// } diff --git a/src/isa/mod.rs b/src/isa/mod.rs new file mode 100644 index 0000000..5e9a7dc --- /dev/null +++ b/src/isa/mod.rs @@ -0,0 +1,32 @@ +pub mod opcodes; + +enum Register { + X0 = 0, + X1 = 1, + X2 = 2, + X3 = 3, + X4 = 4, + X5 = 5, + X6 = 6, + X7 = 7, + X8 = 8, + X9 = 9, + X10 = 10, + X11 = 11, +} + +pub struct Instruction { + word: u32, +} + +impl Instruction { + pub fn new(word: u32) -> Instruction { + Instruction { + word: word, + } + } + + pub fn opcode(&self) -> u32 { + self.word & 0x7F + } +} diff --git a/src/isa/opcodes.rs b/src/isa/opcodes.rs new file mode 100644 index 0000000..0ea7613 --- /dev/null +++ b/src/isa/opcodes.rs @@ -0,0 +1,2 @@ +pub const Branch: u32 = 0x12; +pub const IntegerImmediate: u32 = 0x13; diff --git a/src/lib.rs b/src/lib.rs new file mode 100644 index 0000000..f710c03 --- /dev/null +++ b/src/lib.rs @@ -0,0 +1,9 @@ +mod isa; +mod binary; +mod memory; +mod cache; +mod simulator; + +#[test] +fn it_works() { +} diff --git a/src/memory.rs b/src/memory.rs new file mode 100644 index 0000000..854b0ea --- /dev/null +++ b/src/memory.rs @@ -0,0 +1,21 @@ +use isa::{Instruction}; + +pub struct Memory { + memory: Vec, +} + +impl Memory { + pub fn new(size: usize) -> Memory { + Memory { + memory: Vec::with_capacity(size), + } + } + + pub fn read_word(&self, address: usize) -> Option { + self.memory.get(address).map(Clone::clone) + } + + pub fn read_instruction(&self, pc: usize) -> Option { + self.memory.get(pc).map(Clone::clone).map(Instruction::new) + } +} diff --git a/src/simulator.rs b/src/simulator.rs new file mode 100644 index 0000000..e965686 --- /dev/null +++ b/src/simulator.rs @@ -0,0 +1,58 @@ +use isa; +use binary::{Binary}; +use memory::{Memory}; + +pub struct Simulator<'a> { + binary: Binary<'a>, + num_cores: usize, + memory: Memory, +} + +#[derive(Clone)] +struct Core { + pc: usize, +} + +struct RegisterFile { + registers: [u32; 32], +} + +impl<'a> Simulator<'a> { + pub fn new(num_cores: usize, binary: Binary<'a>) -> Simulator<'a> { + Simulator { + binary: binary, + num_cores: num_cores, + memory: Memory::new(0x20000), + } + } + + pub fn run(&mut self) { + let mut cores = vec![Core { pc: 0x10000, }; self.num_cores]; + // TODO: set up memory, cache, devices + // TODO: map binary into RAM + loop { + for core in cores.iter_mut() { + self.step_core(core); + } + } + } + + fn step_core(&mut self, core: &mut Core) { + if let Some(inst) = self.memory.read_instruction(core.pc) { + match inst.opcode() { + isa::opcodes::Branch => { + + } + isa::opcodes::IntegerImmediate => { + + } + _ => { + + } + } + } + else { + // trap + } + } +} -- cgit v1.2.3