From 1453ffed396ad5f86fc7c3647378301be09206dd Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Fri, 8 Jan 2016 09:34:29 -0700
Subject: Add MemoryInterface.is_address_accessible

---
 src/memory.rs | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src')

diff --git a/src/memory.rs b/src/memory.rs
index 5e630b3..b822fac 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -38,6 +38,8 @@ pub trait MemoryInterface {
     // fn prefetch(&mut self, address: isa::Address);
     // fn invalidate(&mut self, address: isa::Address);
 
+    fn is_address_accessible(&self, address: isa::Address) -> bool;
+
     fn read_word(&mut self, address: isa::Address) -> Result<isa::Word>;
     fn write_word(&mut self, address: isa::Address, value: isa::Word) -> Result<()>;
 
@@ -248,6 +250,10 @@ impl MemoryInterface for Memory {
 
     fn step(&mut self) {}
 
+    fn is_address_accessible(&self, address: isa::Address) -> bool {
+        ((address / 4) as usize) < self.memory.len()
+    }
+
     fn read_word(&mut self, address: isa::Address) -> Result<isa::Word> {
         // memory is word-addressed but addresses are byte-addressed
         self.memory.get((address / 4) as usize)
@@ -359,6 +365,13 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> {
         }
     }
 
+    fn is_address_accessible(&self, address: isa::Address) -> bool {
+        let (tag, index, _) = self.parse_address(address);
+        let ref set = self.cache[index as usize];
+
+        set.valid && set.tag == tag
+    }
+
     fn read_word(&mut self, address: isa::Address) -> Result<isa::Word> {
         let normalized = self.normalize_address(address);
         let (new_tag, _, _) = self.parse_address(address);
-- 
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