From 02e28802676127d1ee71f9a751a0da8f0890204b Mon Sep 17 00:00:00 2001 From: David Li Date: Sat, 9 Jan 2016 15:34:00 -0700 Subject: Add core_id to core, syscalls --- src/simulator.rs | 21 +++++++++++++++------ src/syscall.rs | 2 +- 2 files changed, 16 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/simulator.rs b/src/simulator.rs index c1a300d..f675e58 100644 --- a/src/simulator.rs +++ b/src/simulator.rs @@ -20,7 +20,8 @@ use register_file::RegisterFile; use syscall::SyscallHandler; use trap::Trap; -pub struct Core<'a>{ +pub struct Core<'a> { + id: usize, pc: isa::Address, registers: RegisterFile, stall: u32, @@ -34,16 +35,18 @@ pub struct Core<'a>{ pub struct Simulator<'a, T: SyscallHandler> { cores: Vec>, memory: SharedMemory<'a>, + caches: Vec>, syscall: T, } impl<'a> Core<'a> { // TODO: take Rc> to Memory as well? - pub fn new(entry: isa::Address, sp: isa::Address, + pub fn new(id: usize, entry: isa::Address, sp: isa::Address, cache: SharedMemory<'a>, mmu: Box) -> Core<'a> { let mut registers = RegisterFile::new(); registers.write_word(isa::Register::X2, sp); Core { + id: id, pc: entry, registers: registers, stall: 0, @@ -55,6 +58,10 @@ impl<'a> Core<'a> { } } + pub fn registers(&mut self) -> &mut RegisterFile { + &mut self.registers + } + fn step(&mut self, inst: isa::Instruction, system: &mut SyscallHandler) { let pc = self.pc; @@ -331,7 +338,7 @@ impl<'a> Core<'a> { }, isa::opcodes::SYSTEM => match inst.i_imm() { 0x0 => { - if let Some(trap) = system.syscall(&mut self.registers) { + if let Some(trap) = system.syscall(self.id, &mut self.registers) { self.trap(trap); } } @@ -340,7 +347,8 @@ impl<'a> Core<'a> { } }, _ => { - panic!("Invalid opcode: 0x{:02X} at PC 0x{:X}", inst.opcode(), pc); + panic!("Invalid opcode: 0x{:02X} at PC 0x{:X} in instruction {:?}", + inst.opcode(), pc, inst); } } self.pc += 4; @@ -389,8 +397,9 @@ impl<'a, T: SyscallHandler> Simulator<'a, T> { } fn report(&self) { - for (i, core) in self.cores.iter().enumerate() { - println!("Core {}: stalled {} of {}", i, core.stall_count, core.cycle_count); + for core in self.cores.iter() { + println!("Core {}: stalled {} of {}", + core.id, core.stall_count, core.cycle_count); } } diff --git a/src/syscall.rs b/src/syscall.rs index 41a0fcd..4620e5f 100644 --- a/src/syscall.rs +++ b/src/syscall.rs @@ -19,5 +19,5 @@ use trap; pub trait SyscallHandler { // Can't take cache because syscall can't stall - fn syscall(&mut self, registers: &mut RegisterFile) -> Option; + fn syscall(&mut self, core_id: usize, registers: &mut RegisterFile) -> Option; } -- cgit v1.2.3