From 6dd313d2024c8a0c7a512eca90988ce95b63c6f3 Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Wed, 16 Dec 2015 17:13:38 -0500
Subject: Implement ADDI

---
 src/simulator.rs | 31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)

(limited to 'src/simulator.rs')

diff --git a/src/simulator.rs b/src/simulator.rs
index 8ecf6e7..a258ac1 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -8,18 +8,32 @@ pub struct Simulator {
 }
 
 #[derive(Clone)]
-struct Core {
-    pc: usize,
-}
-
 struct RegisterFile {
     registers: [u32; 32],
 }
 
+#[derive(Clone)]
+struct Core {
+    pc: usize,
+    registers: RegisterFile,
+}
+
 impl RegisterFile {
+    fn new() -> RegisterFile {
+        RegisterFile {
+            registers: [0; 32],
+        }
+    }
+
     fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: u32) {
         // TODO: should be safe to use unchecked index
-        self.registers[reg.into().as_num()] = value;
+        let reg = reg.into();
+        if reg == isa::Register::X0 { return; }
+        self.registers[reg.as_num()] = value;
+    }
+
+    fn read_word<T: Into<isa::Register>>(&mut self, reg: T) -> u32 {
+        self.registers[reg.into().as_num()]
     }
 }
 
@@ -34,7 +48,7 @@ impl Simulator {
     }
 
     pub fn run(&mut self) {
-        let mut cores = vec![Core { pc: 0x10000, }; self.num_cores];
+        let mut cores = vec![Core { pc: 0x10000, registers: RegisterFile::new() }; self.num_cores];
         loop {
             for core in cores.iter_mut() {
                 self.step_core(core);
@@ -50,7 +64,10 @@ impl Simulator {
                 },
                 isa::opcodes::INTEGER_IMMEDIATE => match inst.funct3() {
                     isa::funct3::ADDI => {
-                        println!("ADDI");
+                        let imm = inst.i_imm();
+                        let src: i32 = core.registers.read_word(inst.rs1()) as i32;
+                        core.registers.write_word(inst.rd(), src.wrapping_add(imm) as u32);
+                        println!("After ADDI: {:?} = {}", inst.rd(), core.registers.read_word(inst.rd()) as i32);
                     }
                     _ => {
                         panic!("Invalid integer-immediate funct3code: 0x{:x}", inst.funct3());
-- 
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