From 05ae121c98be750aeca537ded7338c0cbf5f5b4c Mon Sep 17 00:00:00 2001
From: David Li
Date: Fri, 25 Dec 2015 15:15:50 -0700
Subject: Convert PC to u32
---
src/simulator.rs | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
(limited to 'src/simulator.rs')
diff --git a/src/simulator.rs b/src/simulator.rs
index 5eb68e2..127ac8a 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -277,8 +277,9 @@ impl Simulator {
let base = core.registers.read_word(inst.rs1());
let address = ((base as isa::SignedWord) + imm) as isa::Address;
match self.memory.read_word(address) {
- Ok(value) => core.registers.write_word(inst.rd(), value),
- Err(MemoryError::CacheMiss) => return,
+ Ok(value) =>
+ core.registers.write_word(inst.rd(), value),
+ Err(MemoryError::CacheMiss {..}) => return,
Err(MemoryError::InvalidAddress) => {
self.trap(core, Trap::IllegalRead {
address: pc,
@@ -300,7 +301,7 @@ impl Simulator {
let address = ((base as isa::SignedWord) + imm) as isa::Address;
match self.memory.write_word(address, val) {
Ok(()) => (),
- Err(MemoryError::CacheMiss) => return,
+ Err(MemoryError::CacheMiss {..}) => return,
Err(MemoryError::InvalidAddress) => {
self.trap(core, Trap::IllegalWrite {
address: pc,
@@ -319,7 +320,7 @@ impl Simulator {
0x0 => {
// System call
println!("System call {}:", core.registers.read_word(isa::Register::X10));
- let address = core.registers.read_word(isa::Register::X11) as usize;
+ let address = core.registers.read_word(isa::Register::X11);
println!("Argument {:X}: {:?}", address, self.memory.read_word(address));
}
_ => {
--
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