From d916938c7cd8954fa7f6d21815dc11f8aca211f9 Mon Sep 17 00:00:00 2001
From: David Li
Date: Fri, 1 Jan 2016 11:01:38 -0700
Subject: Test use of cache in simulation
---
src/memory.rs | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
(limited to 'src/memory.rs')
diff --git a/src/memory.rs b/src/memory.rs
index 5a30e17..8fdf43d 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -52,7 +52,7 @@ pub trait MemoryInterface {
// fn write_byte(&self, address: isa::Address) -> Result<()>;
}
-pub type SharedMemory = Rc>;
+pub type SharedMemory<'a> = Rc>>;
// TODO: should be a trait
pub struct Mmu {
@@ -86,11 +86,11 @@ struct CacheBlock {
// investigate how LRU is implemented
// TODO: use hashtable for a way?
// TODO: hashtable-based FA cache?
-pub struct DirectMappedCache {
+pub struct DirectMappedCache<'a> {
num_sets: u32,
block_words: u32,
cache: Vec,
- next_level: SharedMemory,
+ next_level: SharedMemory<'a>,
}
impl Memory {
@@ -146,9 +146,9 @@ impl MemoryInterface for Memory {
}
}
-impl DirectMappedCache {
- pub fn new(sets: u32, block_words: u32, next_level: SharedMemory)
- -> DirectMappedCache {
+impl<'a> DirectMappedCache<'a> {
+ pub fn new(sets: u32, block_words: u32, next_level: SharedMemory<'a>)
+ -> DirectMappedCache<'a> {
let set = CacheBlock {
valid: false,
tag: 0,
@@ -190,7 +190,7 @@ impl DirectMappedCache {
}
}
-impl MemoryInterface for DirectMappedCache {
+impl<'a> MemoryInterface for DirectMappedCache<'a> {
fn latency(&self) -> u32 {
100
}
@@ -254,7 +254,7 @@ impl MemoryInterface for DirectMappedCache {
prefetch: false,
cycles_left: stall,
tag: new_tag,
- data: vec![0, self.block_words],
+ data: vec![0; self.block_words as usize],
error: None,
waiting_on: 0,
});
--
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