From 01f161fa1ac86e75524bf038e51a236f0dfb22a6 Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Sun, 3 Jan 2016 13:47:01 -0700
Subject: Add MMU to core

---
 src/memory.rs | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

(limited to 'src/memory.rs')

diff --git a/src/memory.rs b/src/memory.rs
index 9f14700..92aefd5 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -89,7 +89,38 @@ pub trait MemoryInterface {
 pub type SharedMemory<'a> = Rc<RefCell<Box<MemoryInterface + 'a>>>;
 
 pub trait Mmu {
-    fn translate(address: isa::Address) -> isa::Address;
+    fn translate(&self, address: isa::Address) -> isa::Address;
+}
+
+pub struct IdentityMmu {}
+pub struct ReverseMmu {
+    top: isa::Address,
+}
+
+impl IdentityMmu {
+    pub fn new() -> IdentityMmu {
+        IdentityMmu {}
+    }
+}
+
+impl Mmu for IdentityMmu {
+    fn translate(&self, address: isa::Address) -> isa::Address {
+        address
+    }
+}
+
+impl ReverseMmu {
+    pub fn new(top: isa::Address) -> ReverseMmu {
+        ReverseMmu {
+            top: top,
+        }
+    }
+}
+
+impl Mmu for ReverseMmu {
+    fn translate(&self, address: isa::Address) -> isa::Address {
+        self.top - address
+    }
 }
 
 pub struct Memory {
-- 
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