From 55a9ca94d64249280438da9b90186e0a4973f90d Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Wed, 16 Dec 2015 16:15:29 -0500
Subject: Load and recognize a minimal set of instructions

---
 src/isa/funct3.rs  |  8 ++++++++
 src/isa/mod.rs     | 13 ++++++++++++-
 src/isa/opcodes.rs |  6 ++++--
 3 files changed, 24 insertions(+), 3 deletions(-)
 create mode 100644 src/isa/funct3.rs

(limited to 'src/isa')

diff --git a/src/isa/funct3.rs b/src/isa/funct3.rs
new file mode 100644
index 0000000..d9a626a
--- /dev/null
+++ b/src/isa/funct3.rs
@@ -0,0 +1,8 @@
+pub const ADDI: u32 = 0x0;
+pub const SLLI: u32 = 0x1;
+pub const SLTI: u32 = 0x2;
+pub const SLTIU: u32 = 0x3;
+
+pub const LW: u32 = 0x2;
+
+pub const SW: u32 = 0x2;
diff --git a/src/isa/mod.rs b/src/isa/mod.rs
index 5e9a7dc..ac8ce45 100644
--- a/src/isa/mod.rs
+++ b/src/isa/mod.rs
@@ -1,6 +1,7 @@
 pub mod opcodes;
+pub mod funct3;
 
-enum Register {
+pub enum Register {
     X0 = 0,
     X1 = 1,
     X2 = 2,
@@ -15,6 +16,12 @@ enum Register {
     X11 = 11,
 }
 
+impl Register {
+    pub fn as_num(self) -> usize {
+        self as usize
+    }
+}
+
 pub struct Instruction {
     word: u32,
 }
@@ -29,4 +36,8 @@ impl Instruction {
     pub fn opcode(&self) -> u32 {
         self.word & 0x7F
     }
+
+    pub fn funct3(&self) -> u32 {
+        (self.word >> 12) & 0x3
+    }
 }
diff --git a/src/isa/opcodes.rs b/src/isa/opcodes.rs
index 0ea7613..33af0f6 100644
--- a/src/isa/opcodes.rs
+++ b/src/isa/opcodes.rs
@@ -1,2 +1,4 @@
-pub const Branch: u32 = 0x12;
-pub const IntegerImmediate: u32 = 0x13;
+pub const BRANCH: u32 = 0x12;
+pub const INTEGER_IMMEDIATE: u32 = 0x13;
+pub const LOAD: u32 = 0x3;
+pub const STORE: u32 = 0x23;
-- 
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