From 32b7dacc64b70c12096ecb4007465e41f3c2098a Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Tue, 15 Dec 2015 13:38:54 -0500
Subject: Outline the simulator

---
 src/isa/mod.rs     | 32 ++++++++++++++++++++++++++++++++
 src/isa/opcodes.rs |  2 ++
 2 files changed, 34 insertions(+)
 create mode 100644 src/isa/mod.rs
 create mode 100644 src/isa/opcodes.rs

(limited to 'src/isa')

diff --git a/src/isa/mod.rs b/src/isa/mod.rs
new file mode 100644
index 0000000..5e9a7dc
--- /dev/null
+++ b/src/isa/mod.rs
@@ -0,0 +1,32 @@
+pub mod opcodes;
+
+enum Register {
+    X0 = 0,
+    X1 = 1,
+    X2 = 2,
+    X3 = 3,
+    X4 = 4,
+    X5 = 5,
+    X6 = 6,
+    X7 = 7,
+    X8 = 8,
+    X9 = 9,
+    X10 = 10,
+    X11 = 11,
+}
+
+pub struct Instruction {
+    word: u32,
+}
+
+impl Instruction {
+    pub fn new(word: u32) -> Instruction {
+        Instruction {
+            word: word,
+        }
+    }
+
+    pub fn opcode(&self) -> u32 {
+        self.word & 0x7F
+    }
+}
diff --git a/src/isa/opcodes.rs b/src/isa/opcodes.rs
new file mode 100644
index 0000000..0ea7613
--- /dev/null
+++ b/src/isa/opcodes.rs
@@ -0,0 +1,2 @@
+pub const Branch: u32 = 0x12;
+pub const IntegerImmediate: u32 = 0x13;
-- 
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