From 24f8673dce3f8ac8658681f16d856c45dded377a Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Sun, 20 Dec 2015 15:02:13 -0500
Subject: Set LSB of target to 0 in JALR

---
 src/simulator.rs | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/simulator.rs b/src/simulator.rs
index 607a3b5..bf39c5e 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -14,6 +14,7 @@ struct RegisterFile {
 
 #[derive(Clone)]
 struct Core {
+    // TODO: directly encode PC as u32, as architecturally specified
     pc: usize,
     registers: RegisterFile,
     running: bool,
@@ -106,15 +107,17 @@ impl Simulator {
                         core.running = false;
                     }
                     else {
-                        let target = ((pc as i32) + inst.i_imm()) as usize;
+                        let target = (((pc as i32) + inst.i_imm()) & 0xFFFFFFFE) as usize;
                         core.registers.write_word(inst.rd(), pc + 4);
                         core.pc = target;
+                        return;
                     }
                 },
                 isa::opcodes::JAL => {
                     let target = ((pc as i32) + inst.uj_imm()) as usize;
                     core.registers.write_word(inst.rd(), pc + 4);
                     core.pc = target;
+                    return;
                 }
                 isa::opcodes::BRANCH => {
                     
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