| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2015-12-20 | Try handling syscalls | David Li | 1 | -4/+11 | |
| 2015-12-20 | Convert simulator to new type aliases | David Li | 2 | -33/+34 | |
| 2015-12-20 | Introduce type aliases for ISA things | David Li | 4 | -23/+22 | |
| 2015-12-20 | Add Cache API | David Li | 3 | -13/+58 | |
| 2015-12-20 | Fix compile errors | David Li | 2 | -8/+16 | |
| 2015-12-20 | Implement logic for RV32I branch instructions | David Li | 2 | -1/+28 | |
| 2015-12-20 | Set LSB of target to 0 in JALR | David Li | 1 | -1/+4 | |
| 2015-12-20 | Implement JAL, JALR | David Li | 3 | -5/+21 | |
| 2015-12-19 | Implement RV32I integer-immediate instructions | David Li | 5 | -13/+65 | |
| 2015-12-18 | Implement RV32I integer-register instructions | David Li | 7 | -13/+197 | |
| 2015-12-16 | Implement LW | David Li | 1 | -3/+11 | |
| 2015-12-16 | Implement ADDI | David Li | 2 | -7/+95 | |
| 2015-12-16 | Load and recognize a minimal set of instructions | David Li | 7 | -20/+78 | |
| 2015-12-15 | Load hexdump of ELF | David Li | 3 | -13/+81 | |
| 2015-12-15 | Outline the simulator | David Li | 7 | -0/+145 | |
 |
index : rustv | |
| A minimal, intentionally inaccurate RISC-V ISA simulator in Rust |
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