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A minimal, intentionally inaccurate RISC-V ISA simulator in Rust
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2016-01-04
Fix cache sharing bug
David Li
3
-16
/
+26
2016-01-04
Load ELF directly
David Li
3
-38
/
+29
2016-01-04
Implement initializing memory from text/data segments
David Li
4
-11
/
+89
2016-01-04
Add rust-elfloader to tree (needs modification for 32-bit ELF)
David Li
8
-0
/
+1266
2016-01-03
Add MMU to core
David Li
3
-7
/
+49
2016-01-03
Test writing with cache miss
David Li
1
-4
/
+21
2016-01-03
Test reading and writing cache and memory
David Li
1
-0
/
+35
2016-01-03
Write value to cache as well
David Li
1
-35
/
+43
2016-01-03
Fix write_byte, add basic tests
David Li
2
-5
/
+25
2016-01-03
Add write_word, read_byte, write_byte
David Li
1
-6
/
+50
2016-01-02
Use type alias to clean up signatures
David Li
1
-10
/
+7
2016-01-01
Make MMU a trait for API user to implement
David Li
1
-3
/
+2
2016-01-01
Test use of cache in simulation
David Li
3
-12
/
+34
2016-01-01
Finish read_word for cache
David Li
1
-6
/
+17
2015-12-31
Finish DirectMappedCache.step
David Li
2
-19
/
+27
2015-12-31
Sketch impl of cache step
David Li
1
-2
/
+60
2015-12-31
Refactor Core.step slightly
David Li
1
-223
/
+221
2015-12-30
Convert simulator to using cache
David Li
3
-95
/
+118
2015-12-29
Don't give cache ownership of memory
David Li
2
-6
/
+14
2015-12-29
Don't give simulator ownership of binary
David Li
1
-2
/
+3
2015-12-29
Update test for new cache
David Li
3
-9
/
+12
2015-12-28
Specialize to direct-mapped cache
David Li
1
-21
/
+35
2015-12-28
Implement basic cache lookup
David Li
1
-10
/
+27
2015-12-27
Add GPLv3 license
David Li
8
-0
/
+128
2015-12-27
Move tests to test module
David Li
1
-11
/
+16
2015-12-27
Fix and test cache address parsing
David Li
2
-12
/
+26
2015-12-27
Include fetch requests in cache
David Li
2
-7
/
+17
2015-12-26
Reenable jump/branch instructions
David Li
1
-37
/
+39
2015-12-25
Convert PC to u32
David Li
3
-12
/
+38
2015-12-25
Add trait for memory interface
David Li
4
-36
/
+85
2015-12-20
Fix immediate calculation in JAL
David Li
2
-40
/
+42
2015-12-20
Merge branch 'master' of git.lidavidm.me:rustv
David Li
7
-51
/
+150
2015-12-20
Try handling syscalls
David Li
1
-4
/
+11
2015-12-20
Convert simulator to new type aliases
David Li
2
-33
/
+34
2015-12-20
Introduce type aliases for ISA things
David Li
4
-23
/
+22
2015-12-20
Add Cache API
David Li
3
-13
/
+58
2015-12-20
Fix compile errors
David Li
2
-8
/
+16
2015-12-20
Implement logic for RV32I branch instructions
David Li
2
-1
/
+28
2015-12-20
Set LSB of target to 0 in JALR
David Li
1
-1
/
+4
2015-12-20
Implement JAL, JALR
David Li
3
-5
/
+21
2015-12-19
Implement RV32I integer-immediate instructions
David Li
5
-13
/
+65
2015-12-18
Implement RV32I integer-register instructions
David Li
7
-13
/
+197
2015-12-16
Implement LW
David Li
1
-3
/
+11
2015-12-16
Implement ADDI
David Li
2
-7
/
+95
2015-12-16
Load and recognize a minimal set of instructions
David Li
7
-20
/
+78
2015-12-15
Load hexdump of ELF
David Li
3
-13
/
+81
2015-12-15
Outline the simulator
David Li
7
-0
/
+145