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2016-01-01Finish read_word for cacheDavid Li1-6/+17
2015-12-31Finish DirectMappedCache.stepDavid Li2-19/+27
2015-12-31Sketch impl of cache stepDavid Li1-2/+60
2015-12-31Refactor Core.step slightlyDavid Li1-223/+221
2015-12-30Convert simulator to using cacheDavid Li3-95/+118
2015-12-29Don't give cache ownership of memoryDavid Li2-6/+14
2015-12-29Don't give simulator ownership of binaryDavid Li1-2/+3
2015-12-29Update test for new cacheDavid Li3-9/+12
2015-12-28Specialize to direct-mapped cacheDavid Li1-21/+35
2015-12-28Implement basic cache lookupDavid Li1-10/+27
2015-12-27Add GPLv3 licenseDavid Li8-0/+128
2015-12-27Move tests to test moduleDavid Li1-11/+16
2015-12-27Fix and test cache address parsingDavid Li2-12/+26
2015-12-27Include fetch requests in cacheDavid Li2-7/+17
2015-12-26Reenable jump/branch instructionsDavid Li1-37/+39
2015-12-25Convert PC to u32David Li3-12/+38
2015-12-25Add trait for memory interfaceDavid Li4-36/+85
2015-12-20Fix immediate calculation in JALDavid Li2-40/+42
2015-12-20Merge branch 'master' of git.lidavidm.me:rustvDavid Li7-51/+150
2015-12-20Try handling syscallsDavid Li1-4/+11
2015-12-20Convert simulator to new type aliasesDavid Li2-33/+34
2015-12-20Introduce type aliases for ISA thingsDavid Li4-23/+22
2015-12-20Add Cache APIDavid Li3-13/+58
2015-12-20Fix compile errorsDavid Li2-8/+16
2015-12-20Implement logic for RV32I branch instructionsDavid Li2-1/+28
2015-12-20Set LSB of target to 0 in JALRDavid Li1-1/+4
2015-12-20Implement JAL, JALRDavid Li3-5/+21
2015-12-19Implement RV32I integer-immediate instructionsDavid Li5-13/+65
2015-12-18Implement RV32I integer-register instructionsDavid Li7-13/+197
2015-12-16Implement LWDavid Li1-3/+11
2015-12-16Implement ADDIDavid Li2-7/+95
2015-12-16Load and recognize a minimal set of instructionsDavid Li7-20/+78
2015-12-15Load hexdump of ELFDavid Li3-13/+81
2015-12-15Outline the simulatorDavid Li7-0/+145