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AgeCommit message (Expand)AuthorFilesLines
2016-01-07Avoid cache deadlockDavid Li1-2/+2
2016-01-07Implement SH/LH/LHUDavid Li1-4/+10
2016-01-07Implement halfword accessDavid Li2-6/+58
2016-01-07Let API user handle syscallsDavid Li5-69/+164
2016-01-06Bump version to 0.2.50.2.5David Li1-1/+0
2016-01-06Implement LUI, AUIPCDavid Li3-0/+13
2016-01-06Implement LB, SB, LBUDavid Li2-52/+76
2016-01-06Correct s_imm calculationDavid Li1-2/+2
2016-01-06Fix default read_instruction implementationDavid Li1-1/+1
2016-01-06Get rid of Box in memory refsDavid Li3-32/+44
2016-01-05Upload elfloader separatelyDavid Li2-5/+10
2016-01-05Rename elfloader crateDavid Li3-3/+3
2016-01-05Re-export elfloaderDavid Li1-1/+4
2016-01-05Update copyrightDavid Li8-8/+8
2016-01-04Enable loading with address translationDavid Li2-15/+27
2016-01-04Get rid of unused codeDavid Li2-9/+4
2016-01-04Make memory construction from segments a method insteadDavid Li2-22/+7
2016-01-04Fix cache sharing bugDavid Li3-16/+26
2016-01-04Load ELF directlyDavid Li3-38/+29
2016-01-04Implement initializing memory from text/data segmentsDavid Li4-11/+89
2016-01-04Add rust-elfloader to tree (needs modification for 32-bit ELF)David Li8-0/+1266
2016-01-03Add MMU to coreDavid Li3-7/+49
2016-01-03Test writing with cache missDavid Li1-4/+21
2016-01-03Test reading and writing cache and memoryDavid Li1-0/+35
2016-01-03Write value to cache as wellDavid Li1-35/+43
2016-01-03Fix write_byte, add basic testsDavid Li2-5/+25
2016-01-03Add write_word, read_byte, write_byteDavid Li1-6/+50
2016-01-02Use type alias to clean up signaturesDavid Li1-10/+7
2016-01-01Make MMU a trait for API user to implementDavid Li1-3/+2
2016-01-01Test use of cache in simulationDavid Li3-12/+34
2016-01-01Finish read_word for cacheDavid Li1-6/+17
2015-12-31Finish DirectMappedCache.stepDavid Li2-19/+27
2015-12-31Sketch impl of cache stepDavid Li1-2/+60
2015-12-31Refactor Core.step slightlyDavid Li1-223/+221
2015-12-30Convert simulator to using cacheDavid Li3-95/+118
2015-12-29Don't give cache ownership of memoryDavid Li2-6/+14
2015-12-29Don't give simulator ownership of binaryDavid Li1-2/+3
2015-12-29Update test for new cacheDavid Li3-9/+12
2015-12-28Specialize to direct-mapped cacheDavid Li1-21/+35
2015-12-28Implement basic cache lookupDavid Li1-10/+27
2015-12-27Add GPLv3 licenseDavid Li8-0/+128
2015-12-27Move tests to test moduleDavid Li1-11/+16
2015-12-27Fix and test cache address parsingDavid Li2-12/+26
2015-12-27Include fetch requests in cacheDavid Li2-7/+17
2015-12-26Reenable jump/branch instructionsDavid Li1-37/+39
2015-12-25Convert PC to u32David Li3-12/+38
2015-12-25Add trait for memory interfaceDavid Li4-36/+85
2015-12-20Fix immediate calculation in JALDavid Li2-40/+42
2015-12-20Merge branch 'master' of git.lidavidm.me:rustvDavid Li7-51/+150
2015-12-20Try handling syscallsDavid Li1-4/+11