index
:
rustv
master
A minimal, intentionally inaccurate RISC-V ISA simulator in Rust
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
simulator.rs
Age
Commit message (
Expand
)
Author
Files
Lines
2016-01-09
Step caches separately from cores
David Li
1
-2
/
+7
2016-01-09
Add core_id to core, syscalls
David Li
1
-6
/
+15
2016-01-07
Always provide stall report
David Li
1
-6
/
+12
2016-01-07
Avoid cache deadlock
David Li
1
-2
/
+2
2016-01-07
Implement SH/LH/LHU
David Li
1
-4
/
+10
2016-01-07
Let API user handle syscalls
David Li
1
-50
/
+14
2016-01-06
Implement LUI, AUIPC
David Li
1
-0
/
+7
2016-01-06
Implement LB, SB, LBU
David Li
1
-49
/
+67
2016-01-06
Get rid of Box in memory refs
David Li
1
-24
/
+39
2016-01-05
Update copyright
David Li
1
-1
/
+1
2016-01-04
Fix cache sharing bug
David Li
1
-13
/
+17
2016-01-04
Load ELF directly
David Li
1
-6
/
+2
2016-01-03
Add MMU to core
David Li
1
-4
/
+14
2016-01-02
Use type alias to clean up signatures
David Li
1
-10
/
+7
2016-01-01
Test use of cache in simulation
David Li
1
-2
/
+23
2015-12-31
Finish DirectMappedCache.step
David Li
1
-0
/
+1
2015-12-31
Refactor Core.step slightly
David Li
1
-223
/
+221
2015-12-30
Convert simulator to using cache
David Li
1
-78
/
+89
2015-12-29
Don't give simulator ownership of binary
David Li
1
-2
/
+3
2015-12-29
Update test for new cache
David Li
1
-1
/
+1
2015-12-27
Add GPLv3 license
David Li
1
-0
/
+16
2015-12-27
Include fetch requests in cache
David Li
1
-1
/
+1
2015-12-26
Reenable jump/branch instructions
David Li
1
-37
/
+39
2015-12-25
Convert PC to u32
David Li
1
-4
/
+5
2015-12-25
Add trait for memory interface
David Li
1
-18
/
+30
2015-12-20
Fix immediate calculation in JAL
David Li
1
-38
/
+40
2015-12-20
Merge branch 'master' of git.lidavidm.me:rustv
David Li
1
-29
/
+58
2015-12-20
Try handling syscalls
David Li
1
-4
/
+11
2015-12-20
Convert simulator to new type aliases
David Li
1
-22
/
+21
2015-12-20
Introduce type aliases for ISA things
David Li
1
-13
/
+13
2015-12-20
Fix compile errors
David Li
1
-3
/
+3
2015-12-20
Implement logic for RV32I branch instructions
David Li
1
-1
/
+21
2015-12-20
Set LSB of target to 0 in JALR
David Li
1
-1
/
+4
2015-12-20
Implement JAL, JALR
David Li
1
-1
/
+8
2015-12-19
Implement RV32I integer-immediate instructions
David Li
1
-10
/
+57
2015-12-18
Implement RV32I integer-register instructions
David Li
1
-6
/
+143
2015-12-16
Implement LW
David Li
1
-3
/
+11
2015-12-16
Implement ADDI
David Li
1
-7
/
+24
2015-12-16
Load and recognize a minimal set of instructions
David Li
1
-11
/
+38
2015-12-15
Load hexdump of ELF
David Li
1
-4
/
+4
2015-12-15
Outline the simulator
David Li
1
-0
/
+58