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path: root/src/memory.rs
AgeCommit message (Expand)AuthorFilesLines
2016-01-06Get rid of Box in memory refsDavid Li1-1/+1
2016-01-05Update copyrightDavid Li1-1/+1
2016-01-04Enable loading with address translationDavid Li1-6/+6
2016-01-04Get rid of unused codeDavid Li1-8/+3
2016-01-04Make memory construction from segments a method insteadDavid Li1-18/+4
2016-01-04Fix cache sharing bugDavid Li1-1/+5
2016-01-04Implement initializing memory from text/data segmentsDavid Li1-0/+45
2016-01-03Add MMU to coreDavid Li1-1/+32
2016-01-03Write value to cache as wellDavid Li1-35/+43
2016-01-03Fix write_byte, add basic testsDavid Li1-4/+3
2016-01-03Add write_word, read_byte, write_byteDavid Li1-6/+50
2016-01-01Make MMU a trait for API user to implementDavid Li1-3/+2
2016-01-01Test use of cache in simulationDavid Li1-8/+8
2016-01-01Finish read_word for cacheDavid Li1-6/+17
2015-12-31Finish DirectMappedCache.stepDavid Li1-19/+26
2015-12-31Sketch impl of cache stepDavid Li1-2/+60
2015-12-30Convert simulator to using cacheDavid Li1-16/+23
2015-12-29Don't give cache ownership of memoryDavid Li1-3/+6
2015-12-29Update test for new cacheDavid Li1-1/+7
2015-12-28Specialize to direct-mapped cacheDavid Li1-21/+35
2015-12-28Implement basic cache lookupDavid Li1-10/+27
2015-12-27Add GPLv3 licenseDavid Li1-0/+16
2015-12-27Fix and test cache address parsingDavid Li1-12/+12
2015-12-27Include fetch requests in cacheDavid Li1-6/+16
2015-12-25Convert PC to u32David Li1-6/+32
2015-12-25Add trait for memory interfaceDavid Li1-18/+50
2015-12-20Introduce type aliases for ISA thingsDavid Li1-9/+7
2015-12-20Add Cache APIDavid Li1-5/+54
2015-12-18Implement RV32I integer-register instructionsDavid Li1-0/+11
2015-12-16Load and recognize a minimal set of instructionsDavid Li1-4/+11
2015-12-15Outline the simulatorDavid Li1-0/+21