| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2015-12-28 | Implement basic cache lookup | David Li | 1 | -10/+27 | |
| 2015-12-27 | Add GPLv3 license | David Li | 1 | -0/+16 | |
| 2015-12-27 | Fix and test cache address parsing | David Li | 1 | -12/+12 | |
| 2015-12-27 | Include fetch requests in cache | David Li | 1 | -6/+16 | |
| 2015-12-25 | Convert PC to u32 | David Li | 1 | -6/+32 | |
| 2015-12-25 | Add trait for memory interface | David Li | 1 | -18/+50 | |
| 2015-12-20 | Introduce type aliases for ISA things | David Li | 1 | -9/+7 | |
| 2015-12-20 | Add Cache API | David Li | 1 | -5/+54 | |
| 2015-12-18 | Implement RV32I integer-register instructions | David Li | 1 | -0/+11 | |
| 2015-12-16 | Load and recognize a minimal set of instructions | David Li | 1 | -4/+11 | |
| 2015-12-15 | Outline the simulator | David Li | 1 | -0/+21 | |
 |
index : rustv | |
| A minimal, intentionally inaccurate RISC-V ISA simulator in Rust |
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