rustv - A minimal, intentionally inaccurate RISC-V ISA simulator in Rust

Age	Commit message (Collapse)	Author	Files	Lines
2016-01-06	Correct s_imm calculation	David Li	1	-2/+2

2016-01-05	Update copyright	David Li	4	-4/+4

2015-12-27	Add GPLv3 license	David Li	4	-0/+64

2015-12-25	Convert PC to u32	David Li	1	-2/+1

2015-12-25	Add trait for memory interface	David Li	1	-0/+4

2015-12-20	Fix immediate calculation in JAL	David Li	1	-2/+2

2015-12-20	Convert simulator to new type aliases	David Li	1	-11/+13

2015-12-20	Introduce type aliases for ISA things	David Li	1	-0/+2

2015-12-20	Add Cache API	David Li	1	-0/+4

2015-12-20	Fix compile errors	David Li	1	-5/+13

2015-12-20	Implement logic for RV32I branch instructions	David Li	1	-0/+7

2015-12-20	Implement JAL, JALR	David Li	2	-4/+13

2015-12-19	Implement RV32I integer-immediate instructions	David Li	3	-2/+8

2015-12-18	Implement RV32I integer-register instructions	David Li	4	-1/+38

2015-12-16	Implement ADDI	David Li	1	-0/+71

2015-12-16	Load and recognize a minimal set of instructions	David Li	3	-3/+24

2015-12-15	Outline the simulator	David Li	2	-0/+34