rustv - A minimal, intentionally inaccurate RISC-V ISA simulator in Rust

Age	Commit message (Collapse)	Author	Files	Lines
2015-12-27	Move tests to test module	David Li	1	-11/+16

2015-12-27	Fix and test cache address parsing	David Li	2	-12/+26

2015-12-27	Include fetch requests in cache	David Li	2	-7/+17

2015-12-26	Reenable jump/branch instructions	David Li	1	-37/+39

2015-12-25	Convert PC to u32	David Li	3	-12/+38

2015-12-25	Add trait for memory interface	David Li	4	-36/+85

2015-12-20	Fix immediate calculation in JAL	David Li	2	-40/+42

2015-12-20	Merge branch 'master' of git.lidavidm.me:rustv	David Li	7	-51/+150

2015-12-20	Try handling syscalls	David Li	1	-4/+11

2015-12-20	Convert simulator to new type aliases	David Li	2	-33/+34

2015-12-20	Introduce type aliases for ISA things	David Li	4	-23/+22

2015-12-20	Add Cache API	David Li	3	-13/+58

2015-12-20	Fix compile errors	David Li	2	-8/+16

2015-12-20	Implement logic for RV32I branch instructions	David Li	2	-1/+28

2015-12-20	Set LSB of target to 0 in JALR	David Li	1	-1/+4

2015-12-20	Implement JAL, JALR	David Li	3	-5/+21

2015-12-19	Implement RV32I integer-immediate instructions	David Li	5	-13/+65

2015-12-18	Implement RV32I integer-register instructions	David Li	7	-13/+197

2015-12-16	Implement LW	David Li	1	-3/+11

2015-12-16	Implement ADDI	David Li	2	-7/+95

2015-12-16	Load and recognize a minimal set of instructions	David Li	7	-20/+78

2015-12-15	Load hexdump of ELF	David Li	3	-13/+81

2015-12-15	Add README	David Li	1	-0/+3

2015-12-15	Outline the simulator	David Li	9	-0/+151