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-rw-r--r--src/isa/mod.rs2
-rw-r--r--src/lib.rs1
-rw-r--r--src/memory.rs16
-rw-r--r--src/simulator.rs26
4 files changed, 22 insertions, 23 deletions
diff --git a/src/isa/mod.rs b/src/isa/mod.rs
index dd803c5..086df74 100644
--- a/src/isa/mod.rs
+++ b/src/isa/mod.rs
@@ -3,6 +3,8 @@ pub mod funct3;
pub mod funct7;
pub type Word = u32;
+pub type SignedWord = i32;
+pub type Address = usize;
#[derive(Debug, PartialEq)]
pub enum Register {
diff --git a/src/lib.rs b/src/lib.rs
index b3d29aa..fd60531 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,7 +1,6 @@
pub mod isa;
pub mod binary;
pub mod memory;
-pub mod cache;
pub mod simulator;
#[test]
diff --git a/src/memory.rs b/src/memory.rs
index c15bd84..ffe37c4 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -1,8 +1,6 @@
use isa::{self, Instruction};
use binary::{Binary};
-pub type Address = usize;
-
pub struct Memory {
memory: Vec<u32>,
}
@@ -28,7 +26,7 @@ pub struct Cache {
// TODO: refactor impls into a MemoryController(?) trait
impl Memory {
- pub fn new(size: Address, binary: Binary) -> Memory {
+ pub fn new(size: isa::Address, binary: Binary) -> Memory {
let mut memory = binary.words.clone();
if size > memory.len() {
let remainder = size - memory.len();
@@ -39,12 +37,12 @@ impl Memory {
}
}
- pub fn read_word(&self, address: Address) -> Option<isa::Word> {
+ pub fn read_word(&self, address: isa::Address) -> Option<isa::Word> {
// memory is word-addressed but addresses are byte-addressed
self.memory.get(address / 4).map(Clone::clone)
}
- pub fn write_word(&mut self, address: Address, value: isa::Word) -> Option<()> {
+ pub fn write_word(&mut self, address: isa::Address, value: isa::Word) -> Option<()> {
let address = address / 4;
if address >= self.memory.len() {
None
@@ -55,7 +53,7 @@ impl Memory {
}
}
- pub fn read_instruction(&self, pc: Address) -> Option<Instruction> {
+ pub fn read_instruction(&self, pc: isa::Address) -> Option<Instruction> {
self.memory.get(pc / 4).map(Clone::clone).map(Instruction::new)
}
}
@@ -74,15 +72,15 @@ impl Cache {
}
}
- fn read_word(&self, address: Address) -> Option<isa::Word> {
+ fn read_word(&self, address: isa::Address) -> Option<isa::Word> {
None
}
- fn write_word(&mut self, address: Address, value: isa::Word) -> Option<()> {
+ fn write_word(&mut self, address: isa::Address, value: isa::Word) -> Option<()> {
None
}
- fn invalidate(&mut self, address: Address) {
+ fn invalidate(&mut self, address: isa::Address) {
}
}
diff --git a/src/simulator.rs b/src/simulator.rs
index 7e7051c..3b70f3f 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -9,13 +9,13 @@ pub struct Simulator {
#[derive(Clone)]
struct RegisterFile {
- registers: [u32; 32],
+ registers: [isa::Word; 32],
}
#[derive(Clone)]
struct Core {
// TODO: directly encode PC as u32, as architecturally specified
- pc: usize,
+ pc: isa::Address,
registers: RegisterFile,
running: bool,
}
@@ -23,19 +23,19 @@ struct Core {
#[derive(Debug)]
enum Trap {
IllegalInstruction {
- address: usize,
+ address: isa::Address,
instruction: isa::Instruction,
},
IllegalRead {
- address: usize,
+ address: isa::Address,
instruction: isa::Instruction,
memory_address: usize,
},
IllegalWrite {
- address: usize,
+ address: isa::Address,
instruction: isa::Instruction,
- memory_address: usize,
- memory_value: u32,
+ memory_address: isa::Address,
+ memory_value: isa::Word,
}
}
@@ -46,14 +46,14 @@ impl RegisterFile {
}
}
- fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: u32) {
+ fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: isa::Word) {
// TODO: should be safe to use unchecked index
let reg = reg.into();
if reg == isa::Register::X0 { return; }
self.registers[reg.as_num()] = value;
}
- fn read_word<T: Into<isa::Register>>(&mut self, reg: T) -> u32 {
+ fn read_word<T: Into<isa::Register>>(&mut self, reg: T) -> isa::Word {
self.registers[reg.into().as_num()]
}
}
@@ -74,7 +74,7 @@ impl Simulator {
registers: RegisterFile::new(),
running: true,
};
- let mut cores = vec![base_core ; self.num_cores];
+ let mut cores = vec![base_core; self.num_cores];
// hardcode GP
cores[0].registers.write_word(isa::Register::X3, 0x10860);
// hardcode SP
@@ -144,13 +144,13 @@ impl Simulator {
},
isa::opcodes::INTEGER_IMMEDIATE => {
let imm = inst.i_imm();
- let src: i32 = core.registers.read_word(inst.rs1()) as i32;
+ let src = core.registers.read_word(inst.rs1()) as isa::SignedWord;
if let Some(value) = match inst.funct3() {
isa::funct3::ADDI => {
- Some(src.wrapping_add(imm) as u32)
+ Some(src.wrapping_add(imm) as isa::Word)
},
isa::funct3::SLLI => {
- Some((src << inst.shamt()) as u32)
+ Some((src << inst.shamt()) as isa::Word)
},
isa::funct3::SLTI => {
if src < imm {