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-rw-r--r--src/simulator.rs87
1 files changed, 58 insertions, 29 deletions
diff --git a/src/simulator.rs b/src/simulator.rs
index 8142b32..d30ae7c 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -9,12 +9,12 @@ pub struct Simulator {
#[derive(Clone)]
struct RegisterFile {
- registers: [u32; 32],
+ registers: [isa::Word; 32],
}
#[derive(Clone)]
struct Core {
- pc: usize,
+ pc: isa::Address,
registers: RegisterFile,
running: bool,
}
@@ -22,19 +22,19 @@ struct Core {
#[derive(Debug)]
enum Trap {
IllegalInstruction {
- address: usize,
+ address: isa::Address,
instruction: isa::Instruction,
},
IllegalRead {
- address: usize,
+ address: isa::Address,
instruction: isa::Instruction,
- memory_address: usize,
+ memory_address: isa::Address,
},
IllegalWrite {
- address: usize,
+ address: isa::Address,
instruction: isa::Instruction,
- memory_address: usize,
- memory_value: u32,
+ memory_address: isa::Address,
+ memory_value: isa::Word,
}
}
@@ -45,14 +45,14 @@ impl RegisterFile {
}
}
- fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: u32) {
+ fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: isa::Word) {
// TODO: should be safe to use unchecked index
let reg = reg.into();
if reg == isa::Register::X0 { return; }
self.registers[reg.as_num()] = value;
}
- fn read_word<T: Into<isa::Register>>(&mut self, reg: T) -> u32 {
+ fn read_word<T: Into<isa::Register>>(&mut self, reg: T) -> isa::Word {
self.registers[reg.into().as_num()]
}
}
@@ -73,7 +73,7 @@ impl Simulator {
registers: RegisterFile::new(),
running: true,
};
- let mut cores = vec![base_core ; self.num_cores];
+ let mut cores = vec![base_core; self.num_cores];
// hardcode GP
cores[0].registers.write_word(isa::Register::X3, 0x10860);
// hardcode SP
@@ -100,27 +100,56 @@ impl Simulator {
match inst.opcode() {
isa::opcodes::JALR => {
// TODO: assert funct3 is 0
- let target = ((core.registers.read_word(inst.rs1()) as i32) + inst.i_imm()) as u32;
+ let target = ((core.registers.read_word(inst.rs1()) as isa::SignedWord) + inst.i_imm()) as isa::Address;
if target == 0x0 {
// ret
core.running = false;
}
+ else {
+ let target = (((pc as isa::SignedWord) + inst.i_imm()) as isa::Address) & 0xFFFFFFFE;
+ core.registers.write_word(inst.rd(), (pc + 4) as isa::Word);
+ core.pc = target;
+ return;
+ }
},
isa::opcodes::JAL => {
-
+ let target = ((pc as isa::SignedWord) + inst.uj_imm()) as isa::Address;
+ core.registers.write_word(inst.rd(), (pc + 4) as isa::Word);
+ core.pc = target;
+ return;
}
isa::opcodes::BRANCH => {
-
+ let target = ((pc as isa::SignedWord) + inst.sb_imm()) as isa::Address;
+ let rs1 = core.registers.read_word(inst.rs1());
+ let rs2 = core.registers.read_word(inst.rs2());
+ if match inst.funct3() {
+ isa::funct3::BEQ => rs1 == rs2,
+ isa::funct3::BNE => rs1 != rs2,
+ isa::funct3::BLT => (rs1 as isa::SignedWord) < (rs2 as isa::SignedWord),
+ isa::funct3::BGE => (rs1 as isa::SignedWord) > (rs2 as isa::SignedWord),
+ isa::funct3::BLTU => rs1 < rs2,
+ isa::funct3::BGEU => rs1 > rs2,
+ _ => {
+ self.trap(core, Trap::IllegalInstruction {
+ address: pc,
+ instruction: inst,
+ });
+ false
+ }
+ } {
+ core.pc = target;
+ return;
+ }
},
isa::opcodes::INTEGER_IMMEDIATE => {
let imm = inst.i_imm();
- let src: i32 = core.registers.read_word(inst.rs1()) as i32;
+ let src = core.registers.read_word(inst.rs1()) as isa::SignedWord;
if let Some(value) = match inst.funct3() {
isa::funct3::ADDI => {
- Some(src.wrapping_add(imm) as u32)
+ Some(src.wrapping_add(imm) as isa::Word)
},
isa::funct3::SLLI => {
- Some((src << inst.shamt()) as u32)
+ Some((src << inst.shamt()) as isa::Word)
},
isa::funct3::SLTI => {
if src < imm {
@@ -131,7 +160,7 @@ impl Simulator {
}
},
isa::funct3::SLTIU => {
- if (src as u32) < (imm as u32) {
+ if (src as isa::Word) < (imm as isa::Word) {
Some(1)
}
else {
@@ -139,12 +168,12 @@ impl Simulator {
}
},
isa::funct3::XORI => {
- Some((src ^ imm) as u32)
+ Some((src ^ imm) as isa::Word)
},
isa::funct3::SRLI_SRAI => {
match inst.funct7() {
- isa::funct7::SRLI => Some(((src as u32) >> inst.shamt()) as u32),
- isa::funct7::SRAI => Some((src >> inst.shamt()) as u32),
+ isa::funct7::SRLI => Some(((src as isa::Word) >> inst.shamt()) as isa::Word),
+ isa::funct7::SRAI => Some((src >> inst.shamt()) as isa::Word),
_ => {
self.trap(core, Trap::IllegalInstruction {
address: pc,
@@ -155,10 +184,10 @@ impl Simulator {
}
},
isa::funct3::ORI => {
- Some((src | imm) as u32)
+ Some((src | imm) as isa::Word)
},
isa::funct3::ANDI => {
- Some((src & imm) as u32)
+ Some((src & imm) as isa::Word)
},
_ => {
self.trap(core, Trap::IllegalInstruction {
@@ -178,8 +207,8 @@ impl Simulator {
if let Some(value) = match inst.funct3() {
isa::funct3::ADD_SUB => {
match inst.funct7() {
- isa::funct7::ADD_SRL => Some(((src1 as i32).wrapping_add(src2 as i32)) as u32),
- isa::funct7::SUB_SRA => Some(((src1 as i32).wrapping_sub(src2 as i32)) as u32),
+ isa::funct7::ADD_SRL => Some(((src1 as isa::SignedWord).wrapping_add(src2 as isa::SignedWord)) as isa::Word),
+ isa::funct7::SUB_SRA => Some(((src1 as isa::SignedWord).wrapping_sub(src2 as isa::SignedWord)) as isa::Word),
_ => {
self.trap(core, Trap::IllegalInstruction {
address: pc,
@@ -193,7 +222,7 @@ impl Simulator {
Some(src1 << src2_shift)
},
isa::funct3::SLT => {
- if (src1 as i32) < (src2 as i32) {
+ if (src1 as isa::SignedWord) < (src2 as isa::SignedWord) {
Some(1)
}
else {
@@ -214,7 +243,7 @@ impl Simulator {
isa::funct3::SRL_SRA => {
match inst.funct7() {
isa::funct7::ADD_SRL => Some(src1 >> src2_shift),
- isa::funct7::SUB_SRA => Some(((src1 as i32) >> src2_shift) as u32),
+ isa::funct7::SUB_SRA => Some(((src1 as isa::SignedWord) >> src2_shift) as isa::Word),
_ => {
self.trap(core, Trap::IllegalInstruction {
address: pc,
@@ -245,7 +274,7 @@ impl Simulator {
isa::funct3::LW => {
let imm = inst.i_imm();
let base = core.registers.read_word(inst.rs1());
- let address = ((base as i32) + imm) as usize;
+ let address = ((base as isa::SignedWord) + imm) as isa::Address;
if let Some(value) = self.memory.read_word(address) {
core.registers.write_word(inst.rd(), value);
}
@@ -266,7 +295,7 @@ impl Simulator {
let imm = inst.s_imm();
let base = core.registers.read_word(inst.rs1());
let val = core.registers.read_word(inst.rs2());
- let address = ((base as i32) + imm) as usize;
+ let address = ((base as isa::SignedWord) + imm) as isa::Address;
self.memory.write_word(address, val);
}
_ => {