diff options
Diffstat (limited to 'src/isa')
-rw-r--r-- | src/isa/funct3.rs | 14 | ||||
-rw-r--r-- | src/isa/funct7.rs | 2 | ||||
-rw-r--r-- | src/isa/mod.rs | 17 | ||||
-rw-r--r-- | src/isa/opcodes.rs | 6 |
4 files changed, 38 insertions, 1 deletions
diff --git a/src/isa/funct3.rs b/src/isa/funct3.rs index d9a626a..0612844 100644 --- a/src/isa/funct3.rs +++ b/src/isa/funct3.rs @@ -2,6 +2,20 @@ pub const ADDI: u32 = 0x0; pub const SLLI: u32 = 0x1; pub const SLTI: u32 = 0x2; pub const SLTIU: u32 = 0x3; +pub const XORI: u32 = 0x4; +pub const SRLI: u32 = 0x5; +pub const SRAI: u32 = 0x5; +pub const ORI: u32 = 0x6; +pub const ANDI: u32 = 0x7; + +pub const ADD_SUB: u32 = 0x0; +pub const SLL: u32 = 0x1; +pub const SLT: u32 = 0x2; +pub const SLTU: u32 = 0x3; +pub const XOR: u32 = 0x4; +pub const SRL_SRA: u32 = 0x5; +pub const OR: u32 = 0x6; +pub const AND: u32 = 0x7; pub const LW: u32 = 0x2; diff --git a/src/isa/funct7.rs b/src/isa/funct7.rs new file mode 100644 index 0000000..f3446fb --- /dev/null +++ b/src/isa/funct7.rs @@ -0,0 +1,2 @@ +pub const ADD_SRL: u32 = 0x0; +pub const SUB_SRA: u32 = 0x1; diff --git a/src/isa/mod.rs b/src/isa/mod.rs index b34d701..ebfd4e8 100644 --- a/src/isa/mod.rs +++ b/src/isa/mod.rs @@ -1,5 +1,6 @@ pub mod opcodes; pub mod funct3; +pub mod funct7; #[derive(Debug, PartialEq)] pub enum Register { @@ -81,6 +82,7 @@ impl Register { } } +#[derive(Copy, Clone, Debug)] pub struct Instruction { word: u32, } @@ -104,11 +106,26 @@ impl Instruction { (self.word >> 12) & 0x3 } + pub fn funct7(&self) -> u32 { + (self.word >> 25) & 0x7F + } + pub fn rs1(&self) -> Register { Register::from_num((self.word >> 15) & 0x1F) } + pub fn rs2(&self) -> Register { + Register::from_num((self.word >> 20) & 0x1F) + } + pub fn i_imm(&self) -> i32 { (self.word as i32) >> 20 } + + pub fn s_imm(&self) -> i32 { + let word = self.word as i32; + let low = (word >> 7) & 0x1F; + let high = (word >> 25) & 0x7F; + (high << 7) | low + } } diff --git a/src/isa/opcodes.rs b/src/isa/opcodes.rs index 33af0f6..e5763e3 100644 --- a/src/isa/opcodes.rs +++ b/src/isa/opcodes.rs @@ -1,4 +1,8 @@ -pub const BRANCH: u32 = 0x12; +pub const BRANCH: u32 = 0x63; +pub const JALR: u32 = 0x67; +pub const JAL: u32 = 0x68; pub const INTEGER_IMMEDIATE: u32 = 0x13; +pub const INTEGER_REGISTER: u32 = 0x33; pub const LOAD: u32 = 0x3; pub const STORE: u32 = 0x23; +pub const SYSTEM: u32 = 0x73; |