diff options
| -rw-r--r-- | src/cache.rs | 3 | ||||
| -rw-r--r-- | src/memory.rs | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/cache.rs b/src/cache.rs index 8b7145a..417a16d 100644 --- a/src/cache.rs +++ b/src/cache.rs @@ -65,6 +65,7 @@ struct Block { } pub trait EventHandler { + fn block_requested(&self, location: CacheLocation); fn block_fetched(&self, location: CacheLocation); } @@ -72,6 +73,7 @@ pub struct EmptyEventHandler {} impl EventHandler for EmptyEventHandler { fn block_fetched(&self, _: CacheLocation) {} + fn block_requested(&self, _: CacheLocation) {} } // TODO: probably want different caches for different strategies, and @@ -207,6 +209,7 @@ impl<'a, T: EventHandler> MemoryInterface for DirectMappedCache<'a, T> { error: None, waiting_on: 0, }); + self.events.block_requested(location); } else if let Some(ref mut fetch_request) = set.fetch_request { if let Some(ref err) = fetch_request.error { diff --git a/src/memory.rs b/src/memory.rs index 33a9503..2a5b717 100644 --- a/src/memory.rs +++ b/src/memory.rs @@ -126,6 +126,7 @@ pub trait MemoryInterface { pub type SharedMemory<'a> = Rc<RefCell<MemoryInterface + 'a>>; +// TODO: rename to BijectiveMmu? pub trait Mmu { fn translate(&self, address: isa::Address) -> isa::Address; } |