diff options
| -rw-r--r-- | src/isa/mod.rs | 2 | ||||
| -rw-r--r-- | src/lib.rs | 2 | ||||
| -rw-r--r-- | src/memory.rs | 9 | ||||
| -rw-r--r-- | src/simulator.rs | 12 |
4 files changed, 18 insertions, 7 deletions
diff --git a/src/isa/mod.rs b/src/isa/mod.rs index 6c4bfbc..1ac585b 100644 --- a/src/isa/mod.rs +++ b/src/isa/mod.rs @@ -197,7 +197,7 @@ macro_rules! isa_utype { let mut bytes = vec![]; for offset in 0..mem::size_of::<$utype>() { - bytes.push(Byte(((self.0 >> (8 * offset)) & 0xFF) as u8)); + bytes.push(Byte((self.0 >> (8 * offset)) as u8)); } bytes @@ -96,9 +96,11 @@ mod tests { let stall = Err(MemoryError::CacheMiss { stall_cycles: memory.latency(), + retry: true, }); let write_stall = Err(MemoryError::CacheMiss { stall_cycles: memory.latency(), + retry: true, }); let memory_ref = Rc::new(RefCell::new(memory)); diff --git a/src/memory.rs b/src/memory.rs index b9f070b..052ffb7 100644 --- a/src/memory.rs +++ b/src/memory.rs @@ -23,7 +23,10 @@ use isa::{self, Instruction, IsaType}; pub enum MemoryError { InvalidAddress, CacheMiss { + /// How many cycles to stall stall_cycles: u32, + /// Whether the load or store should be retried + retry: bool, }, } @@ -334,7 +337,7 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> { fetch_request.data[offset as usize] = data; fetch_request.waiting_on += 1; }, - Err(MemoryError::CacheMiss { stall_cycles }) => { + Err(MemoryError::CacheMiss { stall_cycles, .. }) => { fetch_request.cycles_left = stall_cycles; continue; }, @@ -401,12 +404,14 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> { fetch_request.error = None; return Err(MemoryError::CacheMiss { - stall_cycles: fetch_request.cycles_left + stall_cycles: fetch_request.cycles_left, + retry: true, }); } Err(MemoryError::CacheMiss { stall_cycles: stall, + retry: true, }) } diff --git a/src/simulator.rs b/src/simulator.rs index 63b5eec..41331ef 100644 --- a/src/simulator.rs +++ b/src/simulator.rs @@ -290,9 +290,11 @@ impl<'a> Core<'a> { match result { Ok(value) => self.registers.write_word(inst.rd(), value), - Err(MemoryError::CacheMiss { stall_cycles }) => { + Err(MemoryError::CacheMiss { stall_cycles, retry }) => { self.stall = stall_cycles - 1; - return; // don't increment PC + if retry { + return; // don't increment PC + } }, Err(MemoryError::InvalidAddress) => { self.trap(Trap::IllegalRead { @@ -325,9 +327,11 @@ impl<'a> Core<'a> { match result { Ok(()) => (), - Err(MemoryError::CacheMiss { stall_cycles }) => { + Err(MemoryError::CacheMiss { stall_cycles, retry }) => { self.stall = stall_cycles - 1; - return; // don't increment PC + if retry { + return; // don't increment PC + } }, Err(MemoryError::InvalidAddress) => { self.trap(Trap::IllegalWrite { |