Implement RV32I integer-register instructions

7 files changed, 197 insertions, 13 deletions

diff --git a/src/isa/funct3.rs b/src/isa/funct3.rs
index d9a626a..0612844 100644
--- a/src/isa/funct3.rs
+++ b/src/isa/funct3.rs
@@ -2,6 +2,20 @@ pub const ADDI: u32 = 0x0;
 pub const SLLI: u32 = 0x1;
 pub const SLTI: u32 = 0x2;
 pub const SLTIU: u32 = 0x3;
+pub const XORI: u32 = 0x4;
+pub const SRLI: u32 = 0x5;
+pub const SRAI: u32 = 0x5;
+pub const ORI: u32 = 0x6;
+pub const ANDI: u32 = 0x7;
+
+pub const ADD_SUB: u32 = 0x0;
+pub const SLL: u32 = 0x1;
+pub const SLT: u32 = 0x2;
+pub const SLTU: u32 = 0x3;
+pub const XOR: u32 = 0x4;
+pub const SRL_SRA: u32 = 0x5;
+pub const OR: u32 = 0x6;
+pub const AND: u32 = 0x7;
 
 pub const LW: u32 = 0x2;
 
diff --git a/src/isa/funct7.rs b/src/isa/funct7.rs
new file mode 100644
index 0000000..f3446fb
--- /dev/null
+++ b/src/isa/funct7.rs
@@ -0,0 +1,2 @@
+pub const ADD_SRL: u32 = 0x0;
+pub const SUB_SRA: u32 = 0x1;
diff --git a/src/isa/mod.rs b/src/isa/mod.rs
index b34d701..ebfd4e8 100644
--- a/src/isa/mod.rs
+++ b/src/isa/mod.rs
@@ -1,5 +1,6 @@
 pub mod opcodes;
 pub mod funct3;
+pub mod funct7;
 
 #[derive(Debug, PartialEq)]
 pub enum Register {
@@ -81,6 +82,7 @@ impl Register {
     }
 }
 
+#[derive(Copy, Clone, Debug)]
 pub struct Instruction {
     word: u32,
 }
@@ -104,11 +106,26 @@ impl Instruction {
         (self.word >> 12) & 0x3
     }
 
+    pub fn funct7(&self) -> u32 {
+        (self.word >> 25) & 0x7F
+    }
+
     pub fn rs1(&self) -> Register {
         Register::from_num((self.word >> 15) & 0x1F)
     }
 
+    pub fn rs2(&self) -> Register {
+        Register::from_num((self.word >> 20) & 0x1F)
+    }
+
     pub fn i_imm(&self) -> i32 {
         (self.word as i32) >> 20
     }
+
+    pub fn s_imm(&self) -> i32 {
+        let word = self.word as i32;
+        let low = (word >> 7) & 0x1F;
+        let high = (word >> 25) & 0x7F;
+        (high << 7) | low
+    }
 }
diff --git a/src/isa/opcodes.rs b/src/isa/opcodes.rs
index 33af0f6..e5763e3 100644
--- a/src/isa/opcodes.rs
+++ b/src/isa/opcodes.rs
@@ -1,4 +1,8 @@
-pub const BRANCH: u32 = 0x12;
+pub const BRANCH: u32 = 0x63;
+pub const JALR: u32 = 0x67;
+pub const JAL: u32 = 0x68;
 pub const INTEGER_IMMEDIATE: u32 = 0x13;
+pub const INTEGER_REGISTER: u32 = 0x33;
 pub const LOAD: u32 = 0x3;
 pub const STORE: u32 = 0x23;
+pub const SYSTEM: u32 = 0x73;
diff --git a/src/lib.rs b/src/lib.rs
index cf0b4be..8a607db 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,9 +1,8 @@
-#![feature(as_slice)]
-mod isa;
-mod binary;
-mod memory;
-mod cache;
-mod simulator;
+pub mod isa;
+pub mod binary;
+pub mod memory;
+pub mod cache;
+pub mod simulator;
 
 #[test]
 fn it_works() {
diff --git a/src/memory.rs b/src/memory.rs
index 3409ed4..b7e3721 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -22,6 +22,17 @@ impl Memory {
         self.memory.get(address / 4).map(Clone::clone)
     }
 
+    pub fn write_word(&mut self, address: usize, value: u32) -> Option<()> {
+        let address = address / 4;
+        if address >= self.memory.len() {
+            None
+        }
+        else {
+            self.memory[address] = value;
+            Some(())
+        }
+    }
+
     pub fn read_instruction(&self, pc: usize) -> Option<Instruction> {
         self.memory.get(pc / 4).map(Clone::clone).map(Instruction::new)
     }
diff --git a/src/simulator.rs b/src/simulator.rs
index 0565ef2..c6d9ace 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -16,6 +16,26 @@ struct RegisterFile {
 struct Core {
     pc: usize,
     registers: RegisterFile,
+    running: bool,
+}
+
+#[derive(Debug)]
+enum Trap {
+    IllegalInstruction {
+        address: usize,
+        instruction: isa::Instruction,
+    },
+    IllegalRead {
+        address: usize,
+        instruction: isa::Instruction,
+        memory_address: usize,
+    },
+    IllegalWrite {
+        address: usize,
+        instruction: isa::Instruction,
+        memory_address: usize,
+        memory_value: u32,
+    }
 }
 
 impl RegisterFile {
@@ -48,18 +68,47 @@ impl Simulator {
     }
 
     pub fn run(&mut self) {
-        let mut cores = vec![Core { pc: 0x10000, registers: RegisterFile::new() }; self.num_cores];
+        let base_core = Core {
+            pc: 0x10000,
+            registers: RegisterFile::new(),
+            running: true,
+        };
+        let mut cores = vec![base_core ; self.num_cores];
+        // hardcode GP
         cores[0].registers.write_word(isa::Register::X3, 0x10860);
+        // hardcode SP
+        cores[0].registers.write_word(isa::Register::X2, 0x7FFC);
         loop {
+            let mut ran = false;
             for core in cores.iter_mut() {
+                if !core.running {
+                    continue;
+                }
                 self.step_core(core);
+                ran = true;
+            }
+            if !ran {
+                println!("All cores are not running, stopping...");
+                break;
             }
         }
     }
 
     fn step_core(&mut self, core: &mut Core) {
-        if let Some(inst) = self.memory.read_instruction(core.pc) {
+        let pc = core.pc;
+        if let Some(inst) = self.memory.read_instruction(pc) {
             match inst.opcode() {
+                isa::opcodes::JALR => {
+                    // TODO: assert funct3 is 0
+                    let target = ((core.registers.read_word(inst.rs1()) as i32) + inst.i_imm()) as u32;
+                    if target == 0x0 {
+                        // ret
+                        core.running = false;
+                    }
+                },
+                isa::opcodes::JAL => {
+                    
+                }
                 isa::opcodes::BRANCH => {
                     
                 },
@@ -68,12 +117,81 @@ impl Simulator {
                         let imm = inst.i_imm();
                         let src: i32 = core.registers.read_word(inst.rs1()) as i32;
                         core.registers.write_word(inst.rd(), src.wrapping_add(imm) as u32);
-                        println!("After ADDI: {:?} = 0x{:X}", inst.rd(), core.registers.read_word(inst.rd()) as i32);
-                    }
+                    },
                     _ => {
                         panic!("Invalid integer-immediate funct3code: 0x{:x}", inst.funct3());
                     }
                 },
+                isa::opcodes::INTEGER_REGISTER => {
+                    let src1 = core.registers.read_word(inst.rs1());
+                    let src2 = core.registers.read_word(inst.rs2());
+                    let src2_shift = src2 & 0x1F;
+                    if let Some(value) = match inst.funct3() {
+                        isa::funct3::ADD_SUB => {
+                            match inst.funct7() {
+                                isa::funct7::ADD_SRL => Some(((src1 as i32).wrapping_add(src2 as i32)) as u32),
+                                isa::funct7::SUB_SRA => Some(((src1 as i32).wrapping_sub(src2 as i32)) as u32),
+                                _ => {
+                                    self.trap(core, Trap::IllegalInstruction {
+                                        address: pc,
+                                        instruction: inst,
+                                    });
+                                    None
+                                }
+                            }
+                        },
+                        isa::funct3::SLL => {
+                            Some(src1 << src2_shift)
+                        },
+                        isa::funct3::SLT => {
+                            if (src1 as i32) < (src2 as i32) {
+                                Some(1)
+                            }
+                            else {
+                                Some(0)
+                            }
+                        },
+                        isa::funct3::SLTU => {
+                            if src1 < src2 {
+                                Some(1)
+                            }
+                            else {
+                                Some(0)
+                            }
+                        },
+                        isa::funct3::XOR => {
+                            Some(src1 ^ src2)
+                        },
+                        isa::funct3::SRL_SRA => {
+                            match inst.funct7() {
+                                isa::funct7::ADD_SRL => Some(src1 >> src2_shift),
+                                isa::funct7::SUB_SRA => Some(((src1 as i32) >> src2_shift) as u32),
+                                _ => {
+                                    self.trap(core, Trap::IllegalInstruction {
+                                        address: pc,
+                                        instruction: inst,
+                                    });
+                                    None
+                                }
+                            }
+                        },
+                        isa::funct3::OR => {
+                            Some(src1 | src2)
+                        },
+                        isa::funct3::AND => {
+                            Some(src1 & src2)
+                        },
+                        _ => {
+                            self.trap(core, Trap::IllegalInstruction {
+                                address: pc,
+                                instruction: inst,
+                            });
+                            None
+                        }
+                    } {
+                        core.registers.write_word(inst.rd(), value);
+                    }
+                },
                 isa::opcodes::LOAD => match inst.funct3() {
                      isa::funct3::LW => {
                          let imm = inst.i_imm();
@@ -83,7 +201,13 @@ impl Simulator {
                              core.registers.write_word(inst.rd(), value);
                              println!("Load to {:?}: 0x{:X}", inst.rd(), value);
                          }
-                         // TODO: trap
+                         else {
+                             self.trap(core, Trap::IllegalRead {
+                                 address: pc,
+                                 instruction: inst,
+                                 memory_address: address,
+                             });
+                         }
                      }
                     _ => {
                         panic!("Invalid load funct3code: 0x{:x}", inst.funct3());
@@ -91,12 +215,20 @@ impl Simulator {
                 },
                 isa::opcodes::STORE => match inst.funct3() {
                      isa::funct3::SW => {
-                        println!("SW");
+                         let imm = inst.s_imm();
+                         let base = core.registers.read_word(inst.rs1());
+                         let val = core.registers.read_word(inst.rs2());
+                         let address = ((base as i32) + imm) as usize;
+                         self.memory.write_word(address, val);
+                         println!("Store to 0x{:X}: 0x{:X}", address, val);
                     }
                     _ => {
                         panic!("Invalid store funct3code: 0x{:x}", inst.funct3());
                     }
                 },
+                isa::opcodes::SYSTEM => {
+                    
+                },
                 _ => {
                     panic!("Invalid opcode: 0x{:02X}", inst.opcode());
                 }
@@ -107,4 +239,9 @@ impl Simulator {
         }
         core.pc += 4;
     }
+
+    fn trap(&mut self, core: &mut Core, trap: Trap) {
+        println!("Trap: {:?}", trap);
+        core.running = false;
+    }
 }